The TimberWolf placement and routing package

Sechen, Carl; Sangiovanni‐Vincentelli, Alberto

doi:10.1109/jssc.1985.1052337

Cited by 427 publications

(147 citation statements)

References 4 publications

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“…There are already several placement tools implemented using simulated annealing [170,171,172,173,95]. Integrating placement into the framework would give the benefit of an even more complex objective function, considering technology parameters regarding area, delay, placeability, routability, power consumption, etc.…”

Section: Open Problemsmentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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Section: Open Problemsmentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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“…We use the wolfe tool within OCT to do the placement and routing. Wolfe in turn calls TimberWolfSC-4.2 [15] to do the placement, and YACR [11] to do the routing. Note that even though the fabric cell concept does not require us to use a channel-based place and route technique, we were constrained to use one.…”

Section: Layout Experimental Resultsmentioning

confidence: 99%

A novel VLSI layout fabric for deep sub-micron applications

Khatri¹,

Mehrotra²,

Brayton³

et al.

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

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We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminates the conventional notion of power and ground routing on the integrated circuit die. Instead, power and ground are essentially "pre-routed" all over the die. By a clever arrangement of power/ground and signal pins, we almost completely eliminate the capacitive effects between signal wires. Additionally, we get a power and ground distribution network with a very low resistance at any point on the die. Another advantage of our scheme is that the arrangement of conductors ensures that onchip inductances are uniformly negligible. Finally, characterization of the circuit delays, capacitances and resistances becomes extremely simple in our scheme, and needs to be done only once for a design.We show how the uniform parasitics of our fabric give rise to a reliable and predictable design. We have implemented our scheme using public domain layout software. Preliminary results show that it holds much promise as the layout methodology of choice in DSM integrated circuit design.

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“…The cxtent of the empty space region equals the common spa" of the two edges. (2) No otha cell edges intersect the. re.ctangulnr* LmyNy spm?…”

Section: Channel Generationmentioning

confidence: 99%

Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

Sechen¹

25th ACM/IEEE, Design Automation Conference.Proceedings 1988.

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The algorithms and the implementation of a new macro/custom cell chipplanning. placement, and global muring package arc presented. The siuudatcd-annealingbased placement algorithm m.=d.S in hvo stages. I" the fust stage. the iuteXO""at 8r.X around theindividual cells is determined using B new dynamic intaconnect ~TCB estimator. The second stage consists of: (1) a channel definition step, using a new channel definition algorithm, (2) a global routing step. using a new global router algorithm. and (3) a placement refinement step. This strategy has produced placements which require very little placement modification during detailed routing. Total interco~nect~lcn~th savings of 8 to 49 percent were achieved in experiments on 9 industrml cxrcmts. Furthermore, circuit-area reductions ranged from 4 to 56 percent versus a variety of other placement methods.

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The TimberWolf placement and routing package

Cited by 427 publications

References 4 publications

Integrated logic synthesis using simulated annealing

Integrated logic synthesis using simulated annealing

A novel VLSI layout fabric for deep sub-micron applications

Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

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