A novel VLSI layout fabric for deep sub-micron applications

Abstract

We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminates the conventional notion of power and ground routing on the integrated circuit die. Instead, power and ground are essentially "pre-routed" all over the die. By a clever arrangement of power/ground and signal pins, we almost completely eliminate the capacitive effects between signal wires. Additionally, we get a power and ground distribution network with a very low resistance at any point on the die. Another advantage of our scheme is that the arrangement of conductors ensures that onchip inductances are uniformly negligible. Finally, characterization of the circuit delays, capacitances and resistances becomes extremely simple in our scheme, and needs to be done only once for a design.We show how the uniform parasitics of our fabric give rise to a reliable and predictable design. We have implemented our scheme using public domain layout software. Preliminary results show that it holds much promise as the layout methodology of choice in DSM integrated circuit design.

Wire placement for crosstalk energy minimization in address buses

“…When considering buses (or any global wire), the most intuitive solution consists of spacing the wires, which tends to reduce crosstalk at the source. Another approach consists of shielding the wires by inserting alternating Î and ground lines between existing wires [6]. Although the latter seems to be promising, the former is more well-accepted because it does not require additional capabilities from existing place and route tools, and will be used as the reference solution for our work.…”

Minimum energy near-threshold network of PLA based design

“…Towards this end, we first explore the effect (in terms of power, delay and energy consumption) of changing VDD and Vbulkn (the body bias of NMOS devices in the PLA) for a single PLA and then use this information to help find an optimum VDD value for a circuit designed using these PLAs. The PLA we use is a precharged NOR-NOR PLA (similar to the ones used in [15,3,16,17,18]). The schematic view of the PLA circuit is shown in Figure 1.…”

“…We address the problem of finding the optimal VDD value for minimum energy consumption in a design scenario where a design is implemented using a network of medium sized Programmable Logic Arrays (PLAs) [3]. This design approach was shown recently to be suitable for implementing structured ASICs with a low-NRE cost [4].…”

Wire planning for performance and yield enhancement

“…Design methods such as signal isolation[l] and signal shielding [2] are targeted to increase predictability of interconnect delay. Other solutions such as metal fill [3], design decompaction [4], layer reassignment [5], placement for yield [6] and routing for yield [7] are targeted for yield improvement.…”