Minimum energy near-threshold network of PLA based design

Jayakumar, Nikhil

doi:10.1109/iccd.2005.75

Cited by 7 publications

(6 citation statements)

References 15 publications

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“…Our simulations were validated in VERILOG, and circuit level characteristics were extracted using SPICE modeling. Recent work [25,26,27,14] suggests that the optimal VDD for minimum energy operation is slightly above V T . The techniques described in this paper are equally applicable for these operating conditions as well.…”

Section: Resultsmentioning

confidence: 98%

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A PLA based asynchronous micropipelining approach for subthreshold circuit design

Jayakumar

Garg

Gamache

et al. 2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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Power consumption is a dominant issue in contemporary circuit design. Sub-threshold circuit design is an appealing means to dramatically reduce this power consumption. However, sub-threshold designs suffer from the drawback of being significantly slower than traditional designs. To reduce the speed gap between sub-threshold and traditional designs, we propose a sub-threshold circuit design approach based on asynchronous micropipelining of a levelized network of PLAs. We describe the handshaking protocol, circuit design and logic synthesis issues in this context. Our preliminary results demonstrate that by using our approach, a design can be sped up by about 7×, with an area penalty of 47%. Further, our approach yields an energy improvement of about 4×, compared to a traditional network of PLA design. Our approach is quite general, and can be applied to traditional circuits as well.

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Section: Resultsmentioning

confidence: 98%

“…It has been shown [14] that we can obtain an improvement in the Energy-Delay product as well, by operating the circuit in the near-subthreshold region.…”

Section: Introductionmentioning

confidence: 98%

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A PLA based asynchronous micropipelining approach for subthreshold circuit design

Jayakumar

Garg

Gamache

et al. 2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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“…The network of PLAs in Ref. [54] is clocked and operates as a single combinational unit: all PLAs are precharged simultaneously, and then start evaluating in a domino fashion until all PLAs have evaluated, and only then can the next precharge-evaluate operation begin. As a result, each PLA spends a substantial amount of idle time in either a fully precharged mode (awaiting input data from its predecessors) or a fully evaluated mode (waiting for its successor PLAs to finish their evaluation).…”

Section: Energy Efficient Asynchronous Techniques For Subthreshold Opmentioning

confidence: 99%

Low Power and Energy Efficient Asynchronous Design

Beerel¹,

Roncken²

2007

Journal of Low Power Electronics

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This paper surveys the most promising low-power and energy-efficient asynchronous design techniques that can lead to substantial advantages over synchronous counterparts. Our discussions cover macro-architectural, micro-architectural, and circuit-level differences between asynchronous and synchronous implementations in a wide range of designs, applications, and domains including microprocessors, application specific designs, and networks on chip.

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“…Delay gets worse, but the overall PDP (Power-Delay Product) improves [17]. It has been shown [18] that we can obtain an improvement in the Energy-Delay product as well, by operating the circuit in the near-sub-threshold region.…”

Section: Advantages and Drawbacks Of Subthreshold Operationmentioning

confidence: 99%

Design of Near-Threshold CMOS Logic Gates

Rani¹,

Kumar²,

Charles³

et al. 2012

VLSICS

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Numerous efforts have made to balance the tradeoff between power consumption, area and speed of a design. While studying the design at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end and high performance with power within limit at the other has not made. One solution to achieve the ultra-low power consumption is to operate the design in subthreshold region. The use of sub-threshold circuit designing in fast and energy efficient circuits is always needed in electronics industry especially in DSP, image processing and arithmetic units in microprocessors, where the low power is the primary concern and the delay can be tolerated. We design a simple CMOS inverter in weak inversion region (sub-threshold) and compare the power consumption with strong inversion region using Cadence 0.18µm Technology.

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Minimum energy near-threshold network of PLA based design

Cited by 7 publications

References 15 publications

A PLA based asynchronous micropipelining approach for subthreshold circuit design

A PLA based asynchronous micropipelining approach for subthreshold circuit design

Low Power and Energy Efficient Asynchronous Design

Design of Near-Threshold CMOS Logic Gates

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