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In this study, a high-frequency floating-type memristor emulator has been presented. The proposed emulator circuit uses a current conveyor transconductance amplifier, second generation current conveyor, three resistors and a grounded capacitor. The presented floating-type memristor can be configured in both incremental and decremental configurations and performs well up to 5 MHz. The equivalent memristor equation is verified by theoretical analysis of the proposed circuit which also includes non-ideal analysis. The theoretical proposition has been verified through personal simulation program with integrated circuit emphasis simulations using TSMC 0.25 μm complementary metal oxide semiconductor technology parameters. Moreover, non-volatility and Monte Carlo simulation have been performed to check the robustness of the circuit. The effectiveness of the presented memristor emulator design has been verified by printed circuit board prototype using commonly available integrated circuits AD844 and CA3080. The experimental results are included, which show good agreement with the theoretical and simulation results. To test the functionalities of the proposed designs, their applications as parallel and serial combinations, high-pass filter and Chua's oscillator have been presented.

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This paper deals with The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology. There by the extremely complex functionality is enabled to be integrated on a single chip. So, transistor size is reduced to few nanometers. By reducing the size drastically some problems are occurred. In that leakage power is one of the disadvantage. By using this stacking technique we are going to reduce the leakage currents.

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.