A PLA based asynchronous micropipelining approach for subthreshold circuit design

Jayakumar, Nikhil; Garg, Rajesh; Gamache, Bruce; Khatri, Sunil P.

doi:10.1145/1146909.1147021

Cited by 16 publications

(7 citation statements)

References 23 publications

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“…DVS helps in reducing the circuit power consumption especially when high speed circuit operation is not desired. Today, VLSI circuits are also operated in the sub-threshold region of operation for a widening class of applications which demand extreme low power consumption and can tolerate larger circuit delays [79,80,81].…”

Section: Iv-d Experimental Resultsmentioning

confidence: 99%

Analysis and Design of Resilient VLSI Circuits

Garg¹

2010

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The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes, combined with lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations and radiationinduced soft errors. Among these noise sources, soft errors (or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as combinational logic circuits. Also, in the DSM era, process variations are increasing at an alarming rate, making it more difficult to design reliable VLSI circuits. Hence, it is important to efficiently design robust VLSI circuits that are resilient to radiation particle strikes and process variations. The work presented in this dissertation presents several analysis and design techniques with the goal of realizing VLSI circuits which are tolerant to radiation particle strikes and process variations.This dissertation consists of two parts. The first part proposes four analysis and two design approaches to address radiation particle strikes. The analysis techniques for the radiation particle strikes include: an approach to analytically determine the pulse width and the pulse shape of a radiation induced voltage glitch in combinational circuits, a technique to model the dynamic stability of SRAMs, and a 3D device-level analysis of the radiation tolerance of voltage scaled circuits. Experimental results demonstrate that the

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Section: Iv-d Experimental Resultsmentioning

confidence: 99%

Analysis and Design of Resilient VLSI Circuits

Garg¹

2010

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“…The authors of [6], [12], [7] proposed the use of a phasedetector and a charge pump to dynamically self-adjust for PVT variations in a sub-threshold design approach for ASICs. Their proposed approach utilized a network of PLAs which share a common NMOS body node.…”

Section: Previous Workmentioning

confidence: 99%

“…In practice, this would lead to significant forward bias of the bulkdrain or bulk-source PN junctions, leading to chip failure. In [6], [12], [7] the Nbulk voltage was limited to 0.4 V to avoid forward biasing of the PN junction. The use of Nbulk and Pbulk bias led to a speed up of 9× according to [8].…”

Section: Previous Workmentioning

confidence: 99%

Look-up Table Design for Deep Sub-threshold through Full-Supply Operation

Abusultan¹,

Khatri²

2014

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

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Field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, the high power consumption of FPGAs (which arises due to their flexible structure), make them less appealing for extreme low power applications. In this paper, we present a design of an FPGA lookup table (LUT), with the goal of seamless operation over a wide band of supply voltages. The same LUT design has the ability to operate at sub-threshold voltage when low power is required, and at higher voltages whenever faster performance is required. The results show that operating the LUT in sub-threshold mode yields a (∼80×) lower power and a (∼4×) lower energy than full supply voltage operation, for a 6-input LUT implemented in a 22nm predictive technology. The key drawback of sub-threshold operation is its susceptibility to process, temperature, and supply voltage (PVT) variations. This paper also presents the design and experimental results for a closed-loop adaptive body biasing mechanism to dynamically cancel global (spacial) as well as local (random) PVT variations. For the same 22nm technology, we demonstrate that the closed-loop adaptive body biasing circuits can allow the FPGA LUT to operate over an operating frequency range that spans an order of magnitude (40 MHz to 1300 MHz). We also show that the closed-loop adaptive body biasing circuits can cancel delay variations due to supply voltage changes, and reduce the effect of process variations on setup and hold times by 1.8× and 2.9× respectively. The dynamic body biasing circuits incur a 3.49% area overhead when designed to each drive a cluster of 25 LUTs.

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“…The asynchronous micropipelined version in Ref. [53] differs in two significant ways from the clocked version. For one, it uses handshake signaling, but more importantly it uses latches to store the PLA input data-thus releasing predecessor PLAs from having to hold the data.…”

Section: Energy Efficient Asynchronous Techniques For Subthreshold Opmentioning

confidence: 99%

Low Power and Energy Efficient Asynchronous Design

Beerel¹,

Roncken²

2007

Journal of Low Power Electronics

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This paper surveys the most promising low-power and energy-efficient asynchronous design techniques that can lead to substantial advantages over synchronous counterparts. Our discussions cover macro-architectural, micro-architectural, and circuit-level differences between asynchronous and synchronous implementations in a wide range of designs, applications, and domains including microprocessors, application specific designs, and networks on chip.

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A PLA based asynchronous micropipelining approach for subthreshold circuit design

Cited by 16 publications

References 23 publications

Analysis and Design of Resilient VLSI Circuits

Analysis and Design of Resilient VLSI Circuits

Look-up Table Design for Deep Sub-threshold through Full-Supply Operation

Low Power and Energy Efficient Asynchronous Design

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