Analysis and Design of Resilient VLSI Circuits

Garg, Rajesh

doi:10.1007/978-1-4419-0931-2

Cited by 36 publications

(8 citation statements)

References 110 publications

(303 reference statements)

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“…where Q is the collected charge, and t f and t r are the fall and rise time, respectively. This is in concordance with a typical model used to simulate the effects of SETs in CMOS technologies, based on introducing double-exponential current pulses in critical nodes of the circuits [17,33].…”

Section: Single Event Transients In Low-noise Amplifierssupporting

confidence: 79%

Single-Event Transients in an IEEE 802.15.4 RF Receiver for Wireless Sensor Networks

Mateos-Angulo

Pino

Mayor-Duarte

et al. 2020

Sensors

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This paper presents a procedure to analyse the effects of radiation in an IEEE 802.15.4 RF receiver for wireless sensor networks (WSNs). Specifically, single-event transients (SETs) represent one of the greatest threats to the adequate performance of electronic communication devices in high-radiation environments. The proposed procedure consists in injecting current pulses in sensitive nodes of the receiver and analysing how they propagate through the different circuits that form the receiver. In order to perform this analysis, a Complementary Metal Oxide Semiconductor (CMOS) low-IF receiver has been designed using a 0.18 μm technology from the foundry UMC. In order to analyse the effect of single-event transients in this receiver, it has been studied how current pulses generated in the low-noise amplifier propagate down the receiver chain. The effect of the different circuits that form the receiver on this kind of pulse has been studied prior to the analysis of the complete receiver. First, the effect of SETs in low-noise amplifiers was analysed. Then, the propagation of pulses through mixers was studied. The effect of filters in the analysed current pulses has also been studied. Regarding the analysis of the designed RF receiver, an amplitude and phase shift was observed under the presence of SETs.

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Section: Single Event Transients In Low-noise Amplifierssupporting

confidence: 79%

Single-Event Transients in an IEEE 802.15.4 RF Receiver for Wireless Sensor Networks

Mateos-Angulo

Pino

Mayor-Duarte

et al. 2020

Sensors

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show abstract

“…The effect of an ion impact can be modeled by a current pulse connected to the drain of the transistor. This current pulse is generally described as a double exponential with the following expression [20,21]:…”

Section: Impacts Modelingmentioning

confidence: 99%

RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers

et al. 2019

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This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 μ m CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain of the transistors. The effects of SET (single event transient) and SEU (single event upset) were analyzed connecting current pulses to the drains of all the transistors and analyzing the amplitude variations and phase shifts obtained at the output nodes. Following this procedure, the most sensitive circuits were detected. This paper proposes a combination of radiation hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy to mitigate the effects of radiation. The proposed modifications make the frequency synthesizer more robust against radiation.

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“…However, the conventional 8T cell is separated nMOSes by n-well and has no common-mode effect. In this simulation, two nMOSes (ND0 and ND1) in the proposed 8T cell and one nMOS (ND1) in the conventional 8T cell were made with 65-nm 3-D device models [11]. The other transistors were based on the PTM 65-nm SPICE model.…”

Section: Synopsys 3-d Tcad Simulationmentioning

confidence: 99%

Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

Yoshimoto

Amashita

Okumura

et al. 2012

IEICE Trans. Electron.

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This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves lowpower operation, which is often preferred for low-power/low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, it is difficult to apply an error correction coding (ECC) technique to it. In this paper, we propose a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We saw that a SEU cross section of nMOS is 3.5-4.5 times higher than that of pMOS (SEU: single event upset; a cross section signifies a sensitive area to soft error effects). By using a soft-error simulator, iRoC TFIT, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The simulator includes soft-error measurement data in a commercial 65-nm process. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented (FIT: failure in time). Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the linear energy transfer (LET) threshold in SEU is also improved by 66% in the proposed 8T SRAM by a common-mode effect.

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Analysis and Design of Resilient VLSI Circuits

Cited by 36 publications

References 110 publications

Single-Event Transients in an IEEE 802.15.4 RF Receiver for Wireless Sensor Networks

Single-Event Transients in an IEEE 802.15.4 RF Receiver for Wireless Sensor Networks

RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers

Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

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