Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

Abstract

This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves lowpower operation, which is often preferred for low-power/low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, it is difficult to apply an error correction coding (ECC) technique to it. In this paper, we propose a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We saw that a SEU cross section of nMOS is 3.5-4.5 times higher than that of pMOS (SEU: single event upset; a cross section signifies a sensitive area to soft error effects). By using a soft-error simulator, iRoC TFIT, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The simulator includes soft-error measurement data in a commercial 65-nm process. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented (FIT: failure in time). Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the linear energy transfer (LET) threshold in SEU is also improved by 66% in the proposed 8T SRAM by a common-mode effect.

A Joint SW/HW Approach for Reducing Register File Vulnerability

“…Furthermore, the ECCs suggested in these approaches only focuses on a single bit-flip correction (as design bounded by power consumption). However, the studies show that transient bit-flips often lead to multiple bit errors that cannot be corrected by a single-bit correcting ECC [Yoshimoto et al 2011]. …”

“…ARRA targets Single Bit Upset (SBU) as well as Multiple Bit Upsets (MBUs) [Yoshimoto et al 2011] as the soft error models. SBU refers to a single bit-flip in a register word.…”