Wire planning for performance and yield enhancement

Abstract

In this papec a wire planning strategy at the layout stage is proposed. The strategy addresses deep submicron (DSM) issues facing both designers and manufacturing engineers. For designers, the proposed method reduces the magnitude and variance of cross-coupling capacitance, making interconnect delay smaller and more predictable. For manufacturing engineers, the method reduces design sensitiviiy to random defects and process variations, thereby increasing yield. These objectives are achieved by directing commercial placement and routing tools to utilize routing resources more evenly over the entire die. Example implementations of the wire planning strategy are demonstrated.

Test strategies for a 40 Gbps framer SoC

“…In previous work it has been noted that relaxing (i.e., increasing) the metal pitch in the technology file of the place and route tools can significantly reduce the susceptibility of a design to defects [20,21,22,23,24]. Often this can be done without a penalty in die area.…”

“…Yield increases owing to relaxed metal pitch have been estimated on some designs to be as high as 15% [23]. For this design, the optimal increase in metal pitch without die area penalty was determined experimentally.…”