Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

Chen, T.; Naffziger, Samuel

doi:10.1109/tvlsi.2003.817120

Cited by 153 publications

(100 citation statements)

References 22 publications

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“…Insertion of circuit elements to compensate for variations of propagation delay has been considered for delays in clock distribution networks [33] and in arbitrary logic gates [44]. Self-calibration techniques such as adaptive body bias and adaptive supply voltage are further methods at the designer's disposal [6]. There are also several techniques on higher abstraction levels including Razor [14] and its variants [25] which aim at achieving energyperformance optimum under process variations.…”

Section: A Variation-aware Designmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE.

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Section: A Variation-aware Designmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

View full text Add to dashboard Cite

show abstract

“…However, the delay for such cases (after backannotating in SPICE), is higher than the target delay £ . These are attributable to errors in the interpolated delay and leakage values computed using the expressions in Equations (1) and (2). The error in the leakage values returned by each of the schemes as opposed to the leakage returned by enumeration is calculated, and the values are averaged for the ten benchmarks, over all process and temperature corners.…”

Section: Based On the Values Inmentioning

confidence: 99%

“…Further, elevated temperatures also lead to an increase in the leakage current. On-chip variations can be categorized as lot-to-lot (L2L), wafer-to-wafer (W2W), die-to-die (D2D), and withindie (WID) variations [2].…”

Section: Introductionmentioning

confidence: 99%

“…Bidirectional adaptive body bias has been shown to reduce the impact of D2D and WID parameter variations on microprocessor frequency and leakage in [2], [11]- [14]. Typically, devices that are slow but do not leak too much can be Forward Body Biased (FBB) to improve the speed, whereas devices that are fast and leaky can be Reverse Body Biased (RBB) to meet the leakage budget.…”

Section: Introductionmentioning

confidence: 99%

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Body Bias Voltage Computations for Process and Temperature Compensation

Kumar

Kim

Sapatnekar

2008

IEEE Trans. VLSI Syst.

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Abstract-With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. These variations can cause the delay and the leakage of the chip to vary significantly from their expected values, thereby affecting the yield. Circuit designers have proposed the use of threshold voltage modulation techniques to pull back the chip to the nominal operational region. One such scheme, known as Adaptive Body Bias (ABB), has become extremely effective in ensuring optimal performance or leakage savings. Our work provides a means to efficiently compute the body bias voltages required for ensuring high performance operation in gigascale systems. We provide a CAD perspective for determining the exact amount of bias voltages that can compensate both temperature and process variations. Mathematical models for delay and leakage based on minimal tester measurements are built, and a nonlinear optimization problem is formulated to ensure highest frequency operation under all conditions, and thereby minimize the overall circuit leakage. Three different algorithms are presented and their accuracies and run-times are compared. The algorithms have been applied to a wide range of process and temperature corners, for a 65nm and a 45nm technology node based process. A suitable implementation mechanism has also been outlined.

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“…ABB has been proposed as an effective approach to compensate for the PV impact on performance and power consumption. It provides the ability to manipulate transistor threshold voltage through the body effect and thus enables either a forward or a reverse body effect to change threshold voltage [21]. Here we use ABB to manipulate the threshold voltage of regular gates that are increased by aging, so that we can compensate for the degradation in delay.…”

mentioning

confidence: 99%

Scalable consistency-based hardware trojan detection and diagnosis

Wei

Potkonjak

2011

2011 5th International Conference on Network and System Security

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Abstract-Hardware Trojans (HTs) have become a major concern in modern IC industry, especially with the fast growth in IC outsourcing. HT detection and diagnosis are challenging due to the huge number of gates in modern IC designs and the high cost of testing. We propose a scalable and efficient HT detection and diagnosis scheme based on segmentation and consistency analysis of the gate-level properties. Furthermore, we develop a HT masking approach that prevents the HTs from functioning using selective device aging. We evaluate our HT detection and diagnosis schemes on a set of ISCAS and ITC benchmarks.

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Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

Cited by 153 publications

References 22 publications

Towards Variation-Aware Test Methods

Towards Variation-Aware Test Methods

Body Bias Voltage Computations for Process and Temperature Compensation

Scalable consistency-based hardware trojan detection and diagnosis

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