Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

Abstract

The algorithms and the implementation of a new macro/custom cell chipplanning. placement, and global muring package arc presented. The siuudatcd-annealingbased placement algorithm m.=d.S in hvo stages. I" the fust stage. the iuteXO""at 8r.X around theindividual cells is determined using B new dynamic intaconnect ~TCB estimator. The second stage consists of: (1) a channel definition step, using a new channel definition algorithm, (2) a global routing step. using a new global router algorithm. and (3) a placement refinement step. This strategy has produced placements which require very little placement modification during detailed routing. Total interco~nect~lcn~th savings of 8 to 49 percent were achieved in experiments on 9 industrml cxrcmts. Furthermore, circuit-area reductions ranged from 4 to 56 percent versus a variety of other placement methods.

The Y architecture for on-chip interconnect: analysis and methodology

“…The initial temperature of the simulated annealing algorithm is specified so that it is far larger than the standard deviation of total wirelength distribution [14]. For each temperature, the number of swaps is on the order of 100 times the number of cells [20]. The new temperature is generated by multiplying the current temperature by α 0 95, which is a relatively large α for simulated annealing [20].…”

“…For each temperature, the number of swaps is on the order of 100 times the number of cells [20]. The new temperature is generated by multiplying the current temperature by α 0 95, which is a relatively large α for simulated annealing [20].…”

Building Rectangular Floorplans–A GraphTheoretical Approach

“…The most notable are: min-cut partitioning [1,2,3], forcedirected placement [4], simulated annealing based placement optimisation [5,6], graph clustering [7], rectangular topology generation [8,9] and the building of graphs for rectangular dualisation [10] [11,12].…”

A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming

“…Seven different constraints are shown in Figure 7 and Table 2 Let n be the number of connections and m the number of transistors, the position to gate, drain and source can be inserted in matrix notation to the horizontal and coordinates X and Y of the nets are given by (8) where i∈T and Δ ni where the connection is located as shown in Figure 8. The matrix to vertical coordinates Q y is composed based on the same idea.…”

“…The simulated annealing [8] is analogous to hardware annealing process. It basically involves perturbing independent variables by random values while the temperature controls the standard deviation used by the random number generator.…”