Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA

Abstract

Fault detection and diagnosis of a Field-Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs. Thus, this paper proposes a new technique that is able to uniquely identify any single stuck-at fault's location along with the type of fault. Also, the presented technique is able to locate any single pair-wise bridging fault and distinguish between the two types of common faults. The presented technique uses the Walsh Code method to significantly reduce the number of test configurations when compared with previous methods. Extensive testing of the proposed method is carried out on a series of ISCAS'89 benchmark circuits being implemented in different FPGA families. From the simulation results, the maximum number of configurations needed for interconnect fault detection and diagnosis is log 2where n is the number of nets under test. It is noted that the proposed method is able to reduce the total number of test configurations by log 2 ðn þ 2Þ when compared with previously published methods available in the literature.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

“…The ADT of interconnect resources attempt to cover all given types of faults on nets, the signal paths constructed from multiple interconnect resources [4,5,19,20,21,22], rather than test each resource individually. Test strategies are categorized into three major types, including coding-based algorithms [2,8,14,15,16,21], SAT/SMT-based algorithms [3,9,17], and ATPG-related approaches [6,9,11,23,24]. Coding-based algorithms generate binary value assignments to the nets in a CUT using deterministic coding algorithms.…”

“…Coding-based algorithms generate binary value assignments to the nets in a CUT using deterministic coding algorithms. In [2,14,16], the Walsh code, a set of incremental binary values, is proposed to cover stuck-at and bridging faults. [8] uses ExHaust, a modified one-hot code to cover dominant bridging faults as a complementary to methods in [2,16].…”

“…In [2,14,16], the Walsh code, a set of incremental binary values, is proposed to cover stuck-at and bridging faults. [8] uses ExHaust, a modified one-hot code to cover dominant bridging faults as a complementary to methods in [2,16]. [21] uses a 1-bit sum function as the coding method, with extra fault propagation requirements on different parts of the nets, to cover stuck-at and bridging faults.…”

“…Field programmable gate array (FPGA) is a programmable device that consists of high density and well-organized logic units and programmable interconnect resources [1,2,3,4,5]. Modern FPGAs manufactured with latest process can contain over fifty billion transistors, and thus, faults within FPGAs are highly probable [1,4,5,6,7].…”

“…Modern FPGAs manufactured with latest process can contain over fifty billion transistors, and thus, faults within FPGAs are highly probable [1,4,5,6,7]. Application-dependent test (ADT) method is an exclusive test method for FPGAs that requires a routed user design as the circuit under test (CUT) [2,3,4,6,8,9,10,11]. It only tests configured resources on the CUT.…”