Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications

Goli, Mehran; Stoppe, Jannis; Drechsler, Rolf

doi:10.23919/date.2017.7927064

Cited by 9 publications

(5 citation statements)

References 14 publications

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“…A part of the static information related to the design's structure is presented in its generated debug symbols (Fig. 2, lines [8][9][10][11][12][13][14][15]. It shows that the design contains a module AT-typeA-initiator with (among others) an initiator socket socket and a member function nb_transport_bw with return type tlm_sync_enum.…”

Section: A Static Information Retrievalmentioning

confidence: 99%

“…In this section, the utility value of the run-time information analysis method is illustrated. The extracted information is used to assist the validation of an ESL design against its formal specification [15]. First, the importance of ESL design validation and the related work in this domain are presented in Section IV-A.…”

Section: Application: Validation Of Esl Designsmentioning

confidence: 99%

“…In case of SystemC designs, in [15] the simulation run is used to generate only one sequence diagram from the runtime log. As the behavior of a design is rarely ever defined using only one single sequence diagram, comparing this to the given specification is difficult.…”

Section: B Validating Esl Designs Against Their Formal Specificationsmentioning

confidence: 99%

“…This reduces the validation complexity as the design might contain several transaction of the same communication protocol. In [15] only the transactions' reference address (transaction ID) is used as key to filter redundant transactions. This may not be sufficient as an initiator module can generate two transactions with the same address implementing different communication protocols (e.g., the transactions are sent to two different target modules through an interconnect).…”

Section: B Validating Esl Designs Against Their Formal Specificationsmentioning

confidence: 99%

“…For these or other situations (e.g., to validate that a given documentation still corresponds to the current state of the implementation), a way to generate a proper model from a given implementation would be desirable. Moreover, a part from the fact that knowing the properties of a given design (both structure and behavior) is necessary to understand it, this information can facilitate other steps of the design process such as debugging, validation, verification, and synthesis of the model [15], [16].…”

mentioning

confidence: 99%

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Automated Nonintrusive Analysis of Electronic System Level Designs

Goli

Stoppe

Drechsler

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Due to the ever increasing complexity of hardware systems, designers strive for higher levels of abstractions in the early stages of the design process. Modeling hardware at the electronic system level (ESL) is one way to address this demand, with the C++-based system modeling framework SystemC and its abstract communication library transaction level modeling (TLM) having become de-facto standards for ESL system design. While the C++ compiler is sufficient to compile and simulate a given ESL design, for tasks of design understanding, debugging, or validation (where access to the details of design's structure and behavior is necessarily required), design needs to be processed by an appropriate tool. This problem is often solved by adding instrumentation code to either the design or the library, usually resulting in incomplete logs, work overhead and/or incompatibilities. This paper introduces an approach that automatically extracts information about both, structure and behavior of SystemC designs and TLM transactions, nonintrusively. The information is retrieved from a given design by running it in debug mode while being connected to a preprogrammed debugger, thus leaving the existing sources and workflows untouched while collecting a vast amount of data without user intervention. Illustrating use cases, value change dump files of the SystemC models' behavior and unified modeling language activity diagrams of transaction protocols are created automatically from simulation runs.

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