Automatic Estimation of Verified Floating-Point Round-Off Errors via Static Analysis

Moscato, Mariano M.; Titolo, Laura; Dutle, Aaron; Muñoz, César

doi:10.1007/978-3-319-66266-4_14

Cited by 44 publications

(44 citation statements)

References 22 publications

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“…This case study serves as a representative example: similar combinations could be constructed for other tools using this paper's approach. Combinations of Gappa [9], Fluctuat [11], FPTaylor [21], or other verification tools [8,14,15] with Herbie could also allow validating Herbie's optimizations. Verification tools could also be used to validate the output of other unsound tools, such as Precimonious [18] and STOKE [20].…”

Section: Discussionmentioning

confidence: 99%

Combining Tools for Optimization and Analysis of Floating-Point Computations

et al. 2018

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Recent renewed interest in optimizing and analyzing floatingpoint programs has lead to a diverse array of new tools for numerical programs. These tools are often complementary, each focusing on a distinct aspect of numerical programming. Building reliable floating point applications typically requires addressing several of these aspects, which makes easy composition essential. This paper describes the composition of two recent floating-point tools: Herbie, which performs accuracy optimization, and Daisy, which performs accuracy verification. We find that the combination provides numerous benefits to users, such as being able to use Daisy to check whether Herbie's unsound optimizations improved the worst-case roundoff error, as well as benefits to tool authors, including uncovering a number of bugs in both tools. The combination also allowed us to compare the different program rewriting techniques implemented by these tools for the first time. The paper lays out a road map for combining other floating-point tools and for surmounting common challenges.

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Section: Discussionmentioning

confidence: 99%

Combining Tools for Optimization and Analysis of Floating-Point Computations

et al. 2018

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“…A second phase performs a statistical refinement to join the precision bindings derived from different input sets. Other tools adopt more advanced techniques but their search space is restricted to standard FP types (e.g., PROMISE [8] and Precimonious [14]), or in other cases they are limited to the analysis of functional expressions (e.g., FPTuner [4] and PRECISA [13]). As a final consideration, all these tool do not enable the analysis of the dynamic range associated to a fixed-format FP type.…”

Section: Related Workmentioning

confidence: 99%

A transprecision floating-point platform for ultra-low power computing

Tagliavini

Mach

Rossi

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In modern low-power embedded platforms, the execution of floating-point (FP) operations emerges as a major contributor to the energy consumption of compute-intensive applications with large dynamic range. Experimental evidence shows that 50% of the energy consumed by a core and its data memory is related to FP computations. The adoption of FP formats requiring a lower number of bits is an interesting opportunity to reduce energy consumption, since it allows to simplify the arithmetic circuitry and to reduce the memory bandwidth required to transfer data between memory and registers by enabling vectorization. From a theoretical point of view, the adoption of multiple FP types perfectly fits with the principle of transprecision computing, allowing fine-grained control of approximation while meeting specified constraints on the precision of final results. In this paper we propose an extended FP type system with complete hardware support to enable transprecision computing on low-power embedded processors, including two standard formats (binary32 and binary16) and two new formats (binary8 and binary16alt). First, we introduce a software library that enables exploration of FP types by tuning both precision and dynamic range of program variables. Then, we present a methodology to integrate our library with an external tool for precision tuning, and experimental results that highlight the clear benefits of introducing the new formats. Finally, we present the design of a transprecision FP unit capable of handling 8-bit and 16-bit operations in addition to standard 32bit operations. Experimental results on FP-intensive benchmarks show that up to 90% of FP operations can be safely scaled down to 8-bit or 16-bit formats. Thanks to precision tuning and vectorization, execution time is decreased by 12% and memory accesses are reduced by 27% on average, leading to a reduction of energy consumption up to 30%. I. INTRODUCTIONNowadays most embedded applications involving numerical computations with large dynamic range are performed using binary64 (double-precision) or binary32 (single-precision) floating-point (FP) formats, described by the IEEE 754 standard [18]. In these applications, the execution of FP operations emerges as a major contributor to the energy consumption. To provide experimental evidence of this insight, we have executed a set of FP-intensive applications on PULPino [7], an open-source ULP microcontroller. Results show that 30% of the energy consumption of the core is actually due to FP operations. Moreover, an additional 20% is spent in moving FP operands from data memory to registers and vice versa. To provide a compromise between energy cost and dynamic range, IEEE 754 introduces a 16-bit format referred to as binary16 (half-precision). The introduction of binary16 represents a first step to increase the energy efficiency of FP computations, but software development flows for ULP systems still lack a methodology to evaluate the effect of reduced-precision FP variables on application requirements. In practice,...

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“…This function is used to compute an implicitly coordinated horizontal resolution direction for the aircraft involved in a pair-wise conflict. [13,21] can be used to compute the round-off error estimation ǫ = 6.4801497501321145 × 10 −12 for expr . PRECiSA is a tool that over-approximates the round-off error of floating-point programs.…”

Section: Theorem 1 (Program Transformation Correctnessmentioning

confidence: 99%

Eliminating Unstable Tests in Floating-Point Programs

Titolo

Muñoz

Feliú

et al. 2019

Logic-Based Program Synthesis and Transformation

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Round-off errors arising from the difference between real numbers and their floating-point representation cause the control flow of conditional floating-point statements to deviate from the ideal flow of the real-number computation. This problem, which is called test instability, may result in a significant difference between the computation of a floating-point program and the expected output in real arithmetic. In this paper, a formally proven program transformation is proposed to detect and correct the effects of unstable tests. The output of this transformation is a floating-point program that is guaranteed to return either the result of the original floating-point program when it can be assured that both its real and its floating-point flows agree or a warning when these flows may diverge. The proposed approach is illustrated with the transformation of the core computation of a polygon containment algorithm developed at NASA that is used in a geofencing system for unmanned aircraft systems.

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Automatic Estimation of Verified Floating-Point Round-Off Errors via Static Analysis

Cited by 44 publications

References 22 publications

Combining Tools for Optimization and Analysis of Floating-Point Computations

Combining Tools for Optimization and Analysis of Floating-Point Computations

A transprecision floating-point platform for ultra-low power computing

Eliminating Unstable Tests in Floating-Point Programs

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