Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GoAhead

Beckhoff, Christian; Koch, Dirk; Torreson, Jim

doi:10.1007/978-3-642-36424-2_26

Cited by 18 publications

(13 citation statements)

References 12 publications

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“…Due to space limitations, the analytical formulation of the MILP constraints is not reported in this paper. Rather, a textual description of their purposes is reported next and the complete formulation is available in an on line appendix 2 .…”

Section: Partitioning and Floorplanningmentioning

confidence: 99%

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC

Seyoum¹,

Pagani²,

Biondi³

et al. 2021

Proceedings of the 36th Annual ACM Symposium on Applied Computing

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Despite its benefits, hardware acceleration under dynamic partial reconfiguration (DPR) has not been fully leveraged by many system designers, mostly due to the complexities of the DPR design flow and the lack of efficient design tools to automate the design process. Furthermore, making such a design approach suitable for real-time embedded systems requires the need for extending the standard DPR design flow with additional design steps, which have to accurately account for the timing behavior of the software and hardware components of the design, as well as of the components of the computing platform (e.g., the reconfiguration interface).To address this problem, this paper presents DART, a tool that fully automates the design flow in a real-time DPR-based system that comprises both software and hardware components. The tool targets the Zynq 7-series and Ultrascale+ FPGA-based SoCs by Xilinx. It aims at alleviating the manual effort required by state-ofthe-art tools while not expecting high expertise in the design of programmable logic components under DPR. To this purpose, it fully automates the partitioning, floorplanning, and implementation (routing and bitstream generation) phases, generating a set of bitstreams starting from a set of tasks annotated with high-level timing requirements. The tool leverages mathematical optimization to solve the partitioning and floorplanning problems, and relies on a set of auto-generated scripts that interact with the vendor tools to mobilize the synthesis and implementation stages. DART has been experimentally evaluated with a case study application from an accelerated image processing system.

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Section: Partitioning and Floorplanningmentioning

confidence: 99%

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC

Seyoum¹,

Pagani²,

Biondi³

et al. 2021

Proceedings of the 36th Annual ACM Symposium on Applied Computing

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show abstract

“…Section 6.3) or by using the differential bitstream methodology available by Xilinx. In the latter case, we need to place the netlist of a reconfigurable module (including place and route information) at the target position of our static system (with the help of the GoAhead [18] tool). Both techniques allow module relocation and replication.…”

Section: Module Generationmentioning

confidence: 99%

Enabling Dynamic System Integration on Maxeler HLS Platforms

Kritikakis

Koch

2020

J Sign Process Syst

Self Cite

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High Level Synthesis (HLS) tools enable application domain experts to implement applications and algorithms on FPGAs. The majority of present FPGA applications is following a stream processing model which is almost entirely implemented statically and not exploiting the benefits enabled by partial reconfiguration. In this paper, we propose a generic approach for implementing and using partial reconfiguration through an HLS design flow for Maxeler platforms. Our flow extracts HLS generated HDL code from the Maxeler compilation process in order to implement a static FPGA infrastructure as well as run-time reconfigurable stream processing modules. As a distinct feature, our infrastructure can accommodate multiple partial modules in a pipeline daisy-chained manner, which aligns directly to Maxeler's dataflow programming paradigm. The benefits of the proposed flow are demonstrated by a case study of a dynamically reconfigurable video processing pipeline delivering 6.4GB/s throughput.

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“…OpenPR and GoAhead can help overcome some of the limitations of the vendor flows, but do not address the high-level/abstract design issues, and hence require FPGA design expertise. GoAhead has recently been supplemented with a feature for automatic floorplanning [Beckhoff et al 2013]. Both these tools manipulate Xilinx Design Language (XDL) files to manipulate the placement of blocker macros.…”

Section: Goahead Tool Flowmentioning

confidence: 99%

FPGA Dynamic and Partial Reconfiguration

2018

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Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows, and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption.

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Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GoAhead

Cited by 18 publications

References 12 publications

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC

Enabling Dynamic System Integration on Maxeler HLS Platforms

FPGA Dynamic and Partial Reconfiguration

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