Automatic interconnection rectification for SoC design verification based on the port order fault model

Abstract

Embedded cores are being increasingly used in large system-on-a-chip (SoC) designs. The high complexity of SoC designs lead the design verification to be a challenge for system integrators. This paper presents an automatic interconnection rectification (AIR) technique based on the port order fault model to detect, diagnose, and correct the misplacements of interconnection that occurred in the integration of a SoC design automatically. The experiments are conducted on combinational and sequential benchmarks. Experimental results show that the AIR can correct the misplaced interconnection exactly within reasonable efforts and, therefore, accelerates the integration verification of SoC designs.

A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams

“…In the method, a graph of interconnects and cores is generated in order to verify the timing criteria at various check points. W. Chunyao [10] investigated an automatic interconnection rectification method by the port order fault model, the method can be used to detect and correct the misplacements of interconnection that occurred in the integration of a SoC design automatically. A. Benso [11] discussed the problem of guaranteeing the compliance of a wrapper architecture to the IEEE Standard 1500, presented a systematic method to build a verification framework for IEEE Standard 1500 compliant cores.…”