The POWER8i processor is the latest RISC (Reduced Instruction Set Computer) microprocessor from IBM. It is fabricated using the company's 22-nm Silicon on Insulator (SOI) technology with 15 layers of metal, and it has been designed to significantly improve both single-thread performance and single-core throughput over its predecessor, the POWER7 A processor. The rate of increase in processor frequency enabled by new silicon technology advancements has decreased dramatically in recent generations, as compared to the historic trend. This has caused many processor designs in the industry to show very little improvement in either single-thread or single-core performance, and, instead, larger numbers of cores are primarily pursued in each generation. Going against this industry trend, the POWER8 processor relies on a much improved core and nest microarchitecture to achieve approximately one-and-a-half times the single-thread performance and twice the single-core throughput of the POWER7 processor in several commercial applications. Combined with a 50% increase in the number of cores (from 8 in the POWER7 processor to 12 in the POWER8 processor), the result is a processor that leads the industry in performance for enterprise workloads. This paper describes the core microarchitecture innovations made in the POWER8 processor that resulted in these significant performance benefits.

The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a multi-core computing platform which consists of general-purpose microprocessor and dual programmable digital signal processor (DSP) cores for multimedia applications. To demonstrate its outstanding performance and energy efficiency, we develop multimedia and image processing applications, such as H.264 decoding and object detection, on this multi-core computing platform. In addition, to evaluate the system performance and energy efficiency, electronic system-level (ESL) design with power information is conducted for the embedded system evaluation. According to the experimental results, the system-level virtual platform can assist the hardware engineers and software engineers to enhance the multi-core platform performance and application efficiency, respectively. The systemlevel design methodology benefits to the embedded multi-core design are discussed.

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because the high complexity of SoC, the dksign verification is a challenge for system integrator. To redGce the verification complexity, the port order fault (POF) modlel has been used for verifying the core-based design [l]. I{, this paper, we present a verification scheme and an automaliic verification pattern generation (AVPG) system based on P(3F model.

Embedded cores are being increasingly used in large system-on-a-chip (SoC) designs. The high complexity of SoC designs lead the design verification to be a challenge for system integrators. This paper presents an automatic interconnection rectification (AIR) technique based on the port order fault model to detect, diagnose, and correct the misplacements of interconnection that occurred in the integration of a SoC design automatically. The experiments are conducted on combinational and sequential benchmarks. Experimental results show that the AIR can correct the misplaced interconnection exactly within reasonable efforts and, therefore, accelerates the integration verification of SoC designs.

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model was proposed. It has been used for verifying core-based designs and the corresponding verification pattern generation has been developed. Here, the authors present an automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) for SoC design verification based on the POF model. On average, the size of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45% smaller and the run time decreases 16% as compared with the previous results of AVPG.