Automatic Memory Reductions for RTL Model Verification

Abstract

We present several techniques for automatically reducing memories in RTL designs. This includes a new memory abstraction algorithm that allows us to greatly reduce the size of memories and a technique based on-term rewriting that further improves the abstraction. In contrast to previously proposed methods for abstracting memories of RTL designs, our methods are general-e.g., they allow us to arbitrarily and directly compare memories-and they are sound and complete-e.g., there are no false positives or negatives. In addition, the combination of our techniques allows us to automatically verify RTL pipelined machine designs beyond the reach of current state-of-the-art methods, as our experimental results show.

A succinct memory model for automated design debugging

“…It preserves the memory semantics by adding additional constraints to the BMC problem. More recently, [10] presents a set of memory abstraction algorithms for use in the verification of RTL models that must be specified within their toolspecific language. Although these memory models significantly reduce the size of the state-space compared to the naïve approach, the number of required constraints to model memory grows quadratically in the size of the unrolling k. This can lead to excessive memory requirements for large error traces.…”

BAT: The Bit-Level Analysis Tool

“…The intuition is that this allows us to compare memories for equality or inequality by comparing the abstract memories directly. To make this sound and efficient, a more sophisticated analysis is required, which is presented in our previous work on memory abstraction [4].…”

“…BAT implements a sound, complete, fully automatic, and efficient memory abstraction algorithm that can deal with an extensional theory of finite bit-vector memories [4]. The use of memory abstraction is crucial in bit-level verification problems as the presence of large memories would otherwise lead to intractable SAT problems.…”

“…BAT is the first bit-level reasoning tool that has been used successfully to verify nontrivial bit-level pipelined machines automatically [4]. Pipelined machine verification entails showing that the pipelined machine refines its instruction set architecture.…”

“…We have been able to use BAT to verify a 32-bit 5 stage pipelined machine in approximately 2 minutes [4]. Key features of BAT that enable the verification of complex systems such as pipelined machines are a fully automatic and efficient algorithm for abstracting bit-level memories [4] and a novel method for generating CNF (Conjunctive Normal Form) from a high-level circuit representation [6].…”