Automatic nonlinear memory power modelling

Schmidt, Eberhard; Jochens, G.; Kruse, Lars; Theeuwen, F.; Nebel, Wolfgang

doi:10.1109/date.2001.915135

Cited by 6 publications

(5 citation statements)

References 2 publications

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“…Components of the RT level, upon which the design is later mapped, are first characterized [3]. The power assessment of the memory also takes place based on a characterization [4].…”

Section: Underlying Techniquementioning

confidence: 99%

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System level optimization and design space exploration for low power

Stammermann

Kruse

Nebel

et al. 2001

Proceedings of the 14th International Symposium on Systems Synthesis - ISSS '01

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We present a software tool for power dissipation analysis and optimization on the algorithmic abstraction level from C/C++ and VHDL descriptions. An analysis is most efficient on such a high level since the influence of design decisions on the power demand increases with increasing abstraction [1]. The ORINOCO  tool enables to compare different but functionally equivalent algorithms and bindings to RT-level architectures with respect to power consumption. The results of the optimized binding can be used to guide synthesis. In the experimental evaluation we compare the predicted optimization trend with synthesized implementations and prove the accuracy of our methodology and tool.

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“…Components of the RT level, upon which the design is later mapped, are first characterized [3]. The power assessment of the memory also takes place based on a characterization [4].…”

Section: Underlying Techniquementioning

confidence: 99%

“…The models may contain parameters of both bit width and architecture. Once generated, models are stored in a library and are available for future analysis and optimization [3,4].…”

Section: Model Generationmentioning

confidence: 99%

System level optimization and design space exploration for low power

Stammermann

Kruse

Nebel

et al. 2001

Proceedings of the 14th International Symposium on Systems Synthesis - ISSS '01

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“…Though there have been several different power estimation techniques [6,9,15,16,3,12,11] and different related tools, such as SimplePower [14], Wattch [1], JouleTrack [13], VPR [10] et al; most of them focus on micro-architecture level power estimation. System designers usually could not utilize these techniques or tools in early design stage, because they may not have enough micro-architecture information, or enough time to run a whole simulation for the design.…”

Section: Introductionmentioning

confidence: 99%

System-Level Early Power Estimation for Memory Subsystem in Embedded Systems

Wang

Zhou

2008

2008 Fifth IEEE International Symposium on Embedded Computing

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Section: Power Modelsmentioning

confidence: 99%

“…In case of standard components these models can be generated by simulation and power characterization based on lower level power analysis tools [6] and appropriate power models [7], [8]. Hence Algorithmic-level power analysis includes the following steps: Architecture estimation (scheduling, allocation, binding of operations and memory accesses, communication architecture estimation including wire length prediction), activation estimation, and power model evaluation.…”

Section: Introductionmentioning

confidence: 99%

Predictable design of low power systems by pre-implementation estimation and optimization

Nebel¹

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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-Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to design iterations many of which could have been avoided if the low level ramifications of high level design decisions, at the Architecture-and Algorithmic-level would have been known before the time consuming and tedious RT-and lower level implementation started. In this contribution we present a System-level design flow and respective EDA support tools for low power designs. We analyze the requirements for such a design technology, which shifts more responsibility to the system architect. We exemplify this approach with a design flow for low power systems. The architecture of an Algorithm-level power estimation tool will be presented together with some use cases based on an EDA product which has been commercially developed from the research results of several collaborative projects funded by the Commission of the European Community. I IntroductionAccording to [1] 85% of all design projects finish late if they finish at all. The same source states that all projects are late by 53% of the originally estimated design time. Gartner/Dataquest [2] reported about the number of design iterations and the design time. From these data we can estimate the average design time for current designs to be some 10 months, the expected design time for next designs to be like 15 months. We can also estimate from this report that an average of 4.7 design iterations is needed to complete a design. Our conclusion is that NRE cost are not determined by the increasing mask cost, but rather by the design c ost, secondly that the design community is obviously pessimistic with regard to the design efforts for new designs and thirdly that the design cost could be significantly reduced if design iterations could be avoided.If we assume that the average employment cost for a design engineer in high cost regions is some US$ 200k and if we further expect an additional cost of US$ 30 k for EDA licenses, about 1/3 rd of the total design cost or some US$ 70 k per design engineer are spent due to unexpected design iterations. These are typically due to late detection of design errors or because design problems are found at a very late stage of the design process. Even worse, these delays often cause missed market opportunities if competition is able to enter the market earlier and gains large market shares during the most profitable market window. A delay in market entry of six months can result in reduced revenues of up to 50%. In conclusion, delays and unnecessary design iterations cost the industry tens of billions of Dollars each year.The reasons for the large number of design iterations are manifold: less predictable semiconductor fabrication processes, more aspects to be considered, complexity of the designs. However, there is one common issue between these reasons: The problems are detected too late! Months of tedious design time had already been spent and many...

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Automatic nonlinear memory power modelling

Cited by 6 publications

References 2 publications

System level optimization and design space exploration for low power

System level optimization and design space exploration for low power

System-Level Early Power Estimation for Memory Subsystem in Embedded Systems

Predictable design of low power systems by pre-implementation estimation and optimization

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