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This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is important that accurate physical information is used during high-level synthesis [1]. We propose a new power optimisation algorithm for RTlevel netlists. The optimisation performs simultaneously slicingtree structure-based floorplanning and functional unit binding and allocation. Since floorplanning, binding and allocation can use the information generated by the other step, the algorithm can greatly optimise the interconnect power. Compared to interconnect unaware power optimised circuits, it shows that interconnect power can be reduced by an average of 41.2 %, while reducing overall power by 24.1 % on an average. The functional unit power remains nearly unchanged. These optimisations are not achieved at the expense of area.

We propose a novel power macro-model which is based on the Hamming-distance of two consecutive input vectors and additional information on the module structure. The model is parameterizable in terms of input bit-widths and can be applied to a wide variety of datapath components. The good trade-off between estimation accuracy, model complexity and flexibility makes the model attractive for power analysis and optimization tasks on a high level of abstraction. Furthermore, a new approach is presented, that allows to calculate the average Hamming-distance distribution of an input data stream. It will be demonstrated, that the application of Hamming-distance distributions, instead of only average values, improves the estimation accuracy for a number of typical DSP-modules and data streams.

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