A new parameterizable power macro-model for datapath components

Abstract

We propose a novel power macro-model which is based on the Hamming-distance of two consecutive input vectors and additional information on the module structure. The model is parameterizable in terms of input bit-widths and can be applied to a wide variety of datapath components. The good trade-off between estimation accuracy, model complexity and flexibility makes the model attractive for power analysis and optimization tasks on a high level of abstraction. Furthermore, a new approach is presented, that allows to calculate the average Hamming-distance distribution of an input data stream. It will be demonstrated, that the application of Hamming-distance distributions, instead of only average values, improves the estimation accuracy for a number of typical DSP-modules and data streams.

Analytical High-Level Power Model for LUT-Based Components

“…Beside this parameter, many models also use Signal distance, which describes the number of input bits that are fixed to logic one in two consecutive input vectors. The models are based on a very large number of low-level simulations, although cer- tain modifications permit a trade-off between the accuracy and the time needed for model characterization [3,4].…”

“…Therefore, a new set of simulations is required for the module characterization each time the module's parameters change. There are some high-level power models that try to avoid this problem by constructing models that are parameterizable in terms of different combinations of input's word-lengths [4,8]. In these cases, the dependency of the models on different input signal statistics is expressed in terms of coefficient values stored in a table, obtained again through extensive simulations aimed to cover a large number of different signal statistics.…”

Binding allocation and floorplanning in low power high-level synthesis

“…In order to determine the power consumption of resources power models describing the power consumption and area of the individual resources at RT level [12] are needed. Interconnect power primarily depends on the wire length of individual wires, the number of vias and the switching activity.…”

Lower bound estimation for low power high-level synthesis

“…The deviations are below 5% in these experiments. In Table 3 the deviations averaged over all resource constraints between the lower bounds and the best bindings are shown if a more accurate power model is applied as a cost function [5]. For comparison, the average deviations for the switching activity cost function are also reported.…”

“…In this paper we apply two different power metrics: The average Hamming distance of consecutive input vectors (switching activity for short) and a characterization based RTL power model [5]. Most HLS for low power algorithms use the switching activity at the inputs of datapath resources or simple functions thereof as a cost function of the power consumption of the design [2,3,4].…”