Binding allocation and floorplanning in low power high-level synthesis

Stammermann, A.; Helms, Domenik; Schulte, Milan; Schulz, Arne; Nebel, Wolfgang

doi:10.1109/iccad.2003.159736

Cited by 33 publications

(26 citation statements)

References 13 publications

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“…SA-based HLS is also in practice and is demonstrated in the recent literature [17,18]. During the optimization process, one solution switches to another by using the perturbation operations in a well-defined way and thus the best solution can be obtained after evaluating a large number of different solution configurations.…”

Section: Simulated Annealing Enginementioning

confidence: 99%

“…High-level synthesis for low power has attracted significant attention [20,21]; however, power savings from using deterministic supply voltages and fixed transistor parameters is not necessarily as effective as expected since process variation introduces a wide range of possible values on these originally fixed values. Physical information has also been included by incorporating floorplanning algorithms into HLS [15,18,19] in order to meet the driving force of deep submicron technologies. The relative location information from floorplanning is useful for determining the correlation of the intra-die variation among functional units; unfortunately, none of the above work makes use of this facility.…”

Section: Related Workmentioning

confidence: 99%

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Guaranteeing performance yield in high-level synthesis

Hung¹,

Wu²,

Xie³

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current high-level synthesis tools, performing task scheduling, resource allocation and binding, may result in unexpected performance discrepancy due to the ignorance of the impact of process variation, which requires a shift in the design paradigm, from today's deterministic design to statistical or probabilistic design. In this paper, we present a variation-aware performance yield-guaranteed high-level synthesis algorithm. The proposed approach integrates high-level synthesis and statistical static timing analysis into a simulated annealing engine to simultaneously explore solution space while meeting design objectives. Our results show that the area reduction is in the average of 14% when 95% performance yield is imposed with the same total completion time constraint.

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Section: Simulated Annealing Enginementioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Guaranteeing performance yield in high-level synthesis

Hung¹,

Wu²,

Xie³

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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“…This change has dramatically complicated both design and synthesis. For this reason, a number of researchers have worked on interconnect-aware high-level-synthesis algorithms [30]- [32]. These approaches typically use a loosely coupled independent floorplanner for physical estimation.…”

mentioning

confidence: 99%

Unified Incremental Physical-Level and High-Level Synthesis

Wang

Dick

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Achieving design closure is one of the biggest challenges for modern very large-scale integration system designers. This problem is exacerbated by the lack of high-level designautomation tools that consider the increasingly important impact of physical features, such as interconnect, on integrated circuit area, performance, and power consumption. Using physical information to guide decisions in the behavioral-level stage of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level-synthesis system. This system integrates high-level and physical-design algorithms to concurrently improve a design's schedule, resource binding, and floorplan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefits of efficiency, stability, and better quality of results. The average CPU time speedup resulting from unifying incremental physical-level and high-level synthesis is 24.72× and area improvement is 13.76%. The low power consumption of a state-of-the-art low-power interconnect-aware high-levelsynthesis algorithm is maintained. The benefits of concurrent behavioral-level and physical-design optimization increased for larger problem instances.Index Terms-Behavioral synthesis, floorplanning, low power design.

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“…Approaches to combine several of these tasks of high-level synthesis into one optimization loop have been proposed [11], [12], [13]. The common feature of these optimization flows is to apply a set of moves on a preliminary design, to evaluate the impact of these moves, and following an optimizing heuristic like, e.g.…”

Section: Fig 2: Target Architecture Templatementioning

confidence: 99%

“…Before evaluating the cost function, they perform a floorplanning step during each iteration. Alternatively [11] use allocation and binding moves followed by a floorplanning for cost estimation, while [12] includes allocation, binding and floorplanning moves into their optimization heuristics (see Fig. 3).…”

Section: Fig 2: Target Architecture Templatementioning

confidence: 99%

Predictable design of low power systems by pre-implementation estimation and optimization

Nebel¹

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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-Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to design iterations many of which could have been avoided if the low level ramifications of high level design decisions, at the Architecture-and Algorithmic-level would have been known before the time consuming and tedious RT-and lower level implementation started. In this contribution we present a System-level design flow and respective EDA support tools for low power designs. We analyze the requirements for such a design technology, which shifts more responsibility to the system architect. We exemplify this approach with a design flow for low power systems. The architecture of an Algorithm-level power estimation tool will be presented together with some use cases based on an EDA product which has been commercially developed from the research results of several collaborative projects funded by the Commission of the European Community. I IntroductionAccording to [1] 85% of all design projects finish late if they finish at all. The same source states that all projects are late by 53% of the originally estimated design time. Gartner/Dataquest [2] reported about the number of design iterations and the design time. From these data we can estimate the average design time for current designs to be some 10 months, the expected design time for next designs to be like 15 months. We can also estimate from this report that an average of 4.7 design iterations is needed to complete a design. Our conclusion is that NRE cost are not determined by the increasing mask cost, but rather by the design c ost, secondly that the design community is obviously pessimistic with regard to the design efforts for new designs and thirdly that the design cost could be significantly reduced if design iterations could be avoided.If we assume that the average employment cost for a design engineer in high cost regions is some US$ 200k and if we further expect an additional cost of US$ 30 k for EDA licenses, about 1/3 rd of the total design cost or some US$ 70 k per design engineer are spent due to unexpected design iterations. These are typically due to late detection of design errors or because design problems are found at a very late stage of the design process. Even worse, these delays often cause missed market opportunities if competition is able to enter the market earlier and gains large market shares during the most profitable market window. A delay in market entry of six months can result in reduced revenues of up to 50%. In conclusion, delays and unnecessary design iterations cost the industry tens of billions of Dollars each year.The reasons for the large number of design iterations are manifold: less predictable semiconductor fabrication processes, more aspects to be considered, complexity of the designs. However, there is one common issue between these reasons: The problems are detected too late! Months of tedious design time had already been spent and many...

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Binding allocation and floorplanning in low power high-level synthesis

Cited by 33 publications

References 13 publications

Guaranteeing performance yield in high-level synthesis

Guaranteeing performance yield in high-level synthesis

Unified Incremental Physical-Level and High-Level Synthesis

Predictable design of low power systems by pre-implementation estimation and optimization

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