Automatic Optimization of Input Split and Bias Voltage in Digitally Controlled Dual-Input Doherty RF PAs

Abstract

Digitally controlled Dual-Input Doherty Power Amplifiers (DIDPAs) are becoming increasingly popular due to the flexible input signal splitting between the main and auxiliary stages. Nevertheless, the presence of many degrees of freedom, e.g., input amplitude split and phase displacement as well as biasing for multiple stages, often involves inefficient trial-and-error procedures to reach a suitable PA performance. This article presents automated parameter setting based on coordinate descent or Bayesian optimizations, demonstrating an improvement in the performance in terms of RF output power and power-added efficiency (PAE) in the presence of broadband-modulated signals, yet maintaining suitable linear behavior for, e.g., communications applications.

A VNA-Based Wideband Measurement System for Large-Signal Characterization of Multiport Circuits

“…Figure 11 reports the same plots as Fig. 10 when applying DIDPA linearization, i.e., running both the outer loop in (1) and the inner loop in (2). The performance results in terms of ACPR, EVM, PAE, and average output power are reported in Table I for both cases (with and without linearization).…”

“…This sweep resulted in the input splitting values (α = 1, ϕ = −30 • ), referred as P0 in the following. In order to emulate this splitting behavior across the BW, these conditions are imposed by implementing the inner loop in (2). For this test, the DUT is excited by a random-phase multi-tone input test signal, whose statistics can be shaped to match 5G signals [18].…”

“…in complex modules with multiple ports and input signals [2]. This includes topologies like Doherty, envelope tracking and load-modulated circuits with active signal injection, where measurements need to be conducted at non-50-Ω interfaces.…”

“…In [33], the dual-input control strategy is implemented based on a model for the peaking amplifier. In [34] and [2], optimization techniques are investigated. In none of these cases, signal control is implemented at the calibrated device under-test (DUT) reference planes, as required for on-wafer MMIC testing at millimeterwave frequencies.…”

A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network

“…CMOS technology has been has attracted significant attention in integrated circuit design due to its low cost of implementation and to achieve the goal of realizing complete system-on-chip (SoC) implementation. CMOS-based PAs have numerous limitations because of their low breakdown voltage, the low-quality factor of passive components, high silicon-substrate loss, and the inaccessibility of back via holes for the ground, in which they restrict the attainable linear output power and efficiency as compared to III-V based PAs such as Gallium Arsenide (GaAs) and Gallium Nitride (GaN)-based PAs [ 1 , 2 , 3 , 4 ]. Myriad performance-improving methods for linearity and efficiency refinement have been implemented for CMOS PAs to address these aforementioned limitations [ 5 , 6 ].…”