Automatic program generation for heterogeneous architectures

Deepika, H. V.; Mangala, N.; Babu, Sarat Chandra

doi:10.1109/icacci.2016.7732032

Cited by 7 publications

(4 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This tool provides hybrid-parallel numerical kernels, intelligent resource management, and truly heterogeneous parallelism for multicore CPUs, Nvidia GPUs, and the Intel Xeon Phi (CPU-GPU-PHI) However, the data partitioning is static and is based on single-number performances of devices. Deepika et al [31] present a tool called OpenCLGen. OpenCLGen is a web-based software to automate OpenCL program generation for Single Kernel on Single Device as well as Multiple Kernels on Multiple Devices.…”

Section: B Programming Models and Tools For Hpcmentioning

confidence: 99%

A Hierarchical Data-Partitioning Algorithm for Performance Optimization of Data-Parallel Applications on Heterogeneous Multi-Accelerator NUMA Nodes

2020

View full text Add to dashboard Cite

Modern HPC platforms are highly heterogeneous with tight integration of multicore CPUs and accelerators (such as Graphics Processing Units, Intel Xeon Phis, or Field-Programmable Gate Arrays) empowering them to address the twin critical concerns of performance and energy efficiency. Due to this inherent characteristic, processing elements contend for shared on-chip resources such as Last Level Cache (LLC), interconnect, etc. and shared nodal resources such as DRAM, PCI-E links, etc., resulting in complexities such as resource contention, non-uniform memory access (NUMA), and accelerator-specific limitations such as limited main memory thereby necessitating support for efficient out-of-card execution. Due to these complexities, the performance profiles of data-parallel applications executing on these platforms are not smooth and deviate significantly from the shapes that allowed state-of-the-art load-balancing algorithms to find optimal solutions. In this paper, we propose a hierarchical two-level data partitioning algorithm minimizing the parallel execution time of data-parallel applications on clusters of h identical nodes where each node has c heterogeneous processors. This algorithm takes as input c discrete speed functions of cardinality m corresponding to the c heterogeneous processors. It does not make any assumptions about the shapes of these functions. Unlike load balancing algorithms, optimal solutions found by the algorithm may not load-balance an application in terms of execution time. The proposed algorithm has low time complexity of O(m 2 × h + m 3 × c 3 ) unlike the state-of-the-art algorithm solving the same problem with the complexity of O(m 3 × c 3 × h 3 ). We also propose an extension of the algorithm for clusters of h non-identical nodes where each node has c heterogeneous processors. We experimentally demonstrate the optimality of our algorithm using two well-known and highly optimized multi-threaded data-parallel applications, matrix-matrix multiplication and 2D fast Fourier transform, on a heterogeneous multi-accelerator NUMA node containing an Intel multicore Haswell CPU, an Nvidia K40c GPU, and an Intel Xeon Phi co-processor and a simulated homogeneous cluster of such nodes.

show abstract

Section: B Programming Models and Tools For Hpcmentioning

confidence: 99%

A Hierarchical Data-Partitioning Algorithm for Performance Optimization of Data-Parallel Applications on Heterogeneous Multi-Accelerator NUMA Nodes

2020

View full text Add to dashboard Cite

show abstract

“…In this study, we propose a method that ensures interworking between an artificial intelligence system and a neural network processing system by supporting the interoperable neural network standard format established by Khronos . We developed a parser for neural networks and data based on NNEF to achieve a convenient configuration for the neural networks used in a cross‐platform.…”

Section: Introductionmentioning

confidence: 99%

Interworking technology of neural network and data among deep learning frameworks

et al. 2019

View full text Add to dashboard Cite

Based on the growing demand for neural network technologies, various neural network inference engines are being developed. However, each inference engine has its own neural network storage format. There is a growing demand for standardization to solve this problem. This study presents interworking techniques for ensuring the compatibility of neural networks and data among the various deep learning frameworks. The proposed technique standardizes the graphic expression grammar and learning data storage format using the Neural Network Exchange Format (NNEF) of Khronos. The proposed converter includes a lexical, syntax, and parser. This NNEF parser converts neural network information into a parsing tree and quantizes data. To validate the proposed system, we verified that MNIST is immediately executed by importing AlexNet's neural network and learned data. Therefore, this study contributes an efficient design technique for a converter that can execute a neural network and learned data in various frameworks regardless of the storage format of each framework.

show abstract

“…The abstractions introduced by OpenCL have been proved that prevent the obtaining of the same efficiency as when using directly the vendor programming models, for several common situations [10]. As a result, many state-of-the-art heterogeneous frameworks and libraries of higher level of abstraction [9,13,8,18,3,17], that rely on OpenCL as execution layer, typically inherit some of these problems.…”

Section: Introductionmentioning

confidence: 99%

Supporting the Xeon Phi Coprocessor in a Heterogeneous Programming Model

Moreton-Fernandez

Rodriguez-Gutiez

González-Escribano

et al. 2017

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Supercomputers are becoming more heterogeneous. They are composed by several machines with different computation capabilities and different kinds and families of accelerators, such as GPUs or Intel Xeon Phi coprocessors. Programming these machines is a hard task, that requires a deep study of the architectural details, for exploiting efficiently each computational unit. In this paper, we present an extension of a heterogeneous programming model, in order to also support Intel Xeon Phi coprocessors. This contribution extends an existing heterogeneous programming library, by taking advantage of both the GPU communication model and the CPU execution model of the original library. Our experimental results show that using our approach, the programming effort needed for changing the target devices is highly reduced, by for example reusing the 97% of the code between a GPU implementation and a Xeon Phi implementation for the Mandelbrot benchmark.

show abstract

Automatic program generation for heterogeneous architectures

Cited by 7 publications

References 23 publications

A Hierarchical Data-Partitioning Algorithm for Performance Optimization of Data-Parallel Applications on Heterogeneous Multi-Accelerator NUMA Nodes

A Hierarchical Data-Partitioning Algorithm for Performance Optimization of Data-Parallel Applications on Heterogeneous Multi-Accelerator NUMA Nodes

Interworking technology of neural network and data among deep learning frameworks

Supporting the Xeon Phi Coprocessor in a Heterogeneous Programming Model

Contact Info

Product

Resources

About