Automatic property generation for the formal verification of bus bridges

Soeken, Mathias; Kühne, Ulrich; Freibothe, Martin; Fe, Gorschwin; Drechsler, Rolf

doi:10.1109/ddecs.2011.5783129

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…Designer-guided approaches [32], [33] require manual effort. Automatic generation of properties is usually incomplete and depends on abstract design descriptions [34] or models [35], or analysis of simulation traces [36], which may be difficult. In contrast, we have general completeness results for A-QED 2 .…”

Section: Related Workmentioning

confidence: 99%

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay,

Lonsing,

Piccolboni

et al. 2021

Preprint

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Hardware accelerators (HAs) are essential building blocks for fast and energy-efficient computing systems. Accelerator Quick Error Detection (A-QED) is a recent formal technique which uses Bounded Model Checking for pre-silicon verification of HAs. A-QED checks an HA for self-consistency, i.e., whether identical inputs within a sequence of operations always produce the same output. Under modest assumptions, A-QED is both sound and complete. However, as is well-known, large design sizes significantly limit the scalability of formal verification, including A-QED. We overcome this scalability challenge through a new decomposition technique for A-QED, called A-QED with Decomposition (A-QED 2 ). A-QED 2 systematically decomposes an HA into smaller, functional sub-modules, called sub-accelerators, which are then verified independently using A-QED. We prove completeness of A-QED 2 ; in particular, if the full HA under verification contains a bug, then A-QED 2 ensures detection of that bug during A-QED verification of the corresponding subaccelerators. Results on over 100 (buggy) versions of a wide variety of HAs with millions of logic gates demonstrate the effectiveness and practicality of A-QED 2 . This article will appear in the proceedings of Formal Methods in Computer-Aided Design (FMCAD 2021).

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Section: Related Workmentioning

confidence: 99%

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay,

Lonsing,

Piccolboni

et al. 2021

Preprint

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show abstract

“…The idea of auto generating test cases from higher level requirements has been the subject of intensive study in both the academia and industry [18,19,20]. Creating properties for formal verification from higher level requirements, has been performed manually [21,10], through patterns [22], and automatically [23,24]. The unique contribution of our work is a method for automatically exporting high-level requirements from a system-level reasoning framework as property observers in a component-level modeling framework.…”

Section: Related Workmentioning

confidence: 99%

From Design Contracts to Component Requirements Verification

Liu

Backes

Cofer

et al. 2016

Lecture Notes in Computer Science

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During the development and verification of complex airborne systems, a variety of languages and development environments are used for different levels of the system hierarchy. As a result, there may be manual steps to translate requirements between these different environments. This paper presents a tool-supported export technique that translates high-level requirements from the software architecture modeling environment into observers of requirements that can be used for verification in the software component environment. This allows efficient verification that the component designs comply with their high-level requirements. It also provides an automated tool chain supporting formal verification from system requirements down to low-level software requirements that is consistent with certification guidance for avionics systems. The effectiveness of the technique has been evaluated and demonstrated on a medical infusion pump and an aircraft wheel braking system.

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An Overview on Formal Techniques for Understanding Digital Hardware Designs

Fey

2018

2018 7th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO)

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Automatic property generation for the formal verification of bus bridges

Cited by 3 publications

References 9 publications

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

From Design Contracts to Component Requirements Verification

An Overview on Formal Techniques for Understanding Digital Hardware Designs

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