This paper proposes a verification flow for mixed-signal circuits. The presented flow is based on 'bounded model checking', a formal verification method. The behavior of the analog parts of a mixed-signal circuit is described with the help of rational numbers within the circuit description and in the properties, respectively. Our implemented Property-Checker checks formal properties for a given mixed-signal circuit design over a finite interval of time. The internal representation of the rational numbers has an almost arbitrary accuracy. By using the presented flow, the quasi-static behavior of a mixed-signal circuit can be exhaustively verified

No abstract

In this article, a verification methodology for mixed-signal Circuits is presented that can easily be integrated into industrial design flows. The proposed verification methodology is based on formal verification methods. A VHDL behavioral description of a mixed-signal circuit is transformed into a discrete model and then verified using well-established tools from formal digital verification. Using the presented methodology, a much higher coverage of the functionality of a mixed-signal circuit can be achieved than with simulation based verification methods. The approach has already been successfully applied to industrial mixed-signal circuits

No abstract