Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking

Abstract

In this article, a verification methodology for mixed-signal Circuits is presented that can easily be integrated into industrial design flows. The proposed verification methodology is based on formal verification methods. A VHDL behavioral description of a mixed-signal circuit is transformed into a discrete model and then verified using well-established tools from formal digital verification. Using the presented methodology, a much higher coverage of the functionality of a mixed-signal circuit can be achieved than with simulation based verification methods. The approach has already been successfully applied to industrial mixed-signal circuits

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

“…For instance, the model checking of analog circuits for the specification of time constraints was discussed [17], an approach of defining time-based specifications was introduced. For the verification of mixed-signal circuits, the behavioral description of the mixed-signal circuit was transformed into a discrete model [18], and the verification was performed by formal digital verification technique. The static verification method was proposed [19], the method can verify the proper integration for the analog and mixed-signal macro-blocks into an integrated circuit, and the validity of the interconnections between the blocks was verified.…”