Formal Verification of the Quasi-Static Behavior of Mixed-Signal Circuits by Property Checking

Freibothe, Martin; Schönherr, Jens; Straube, Bernd

doi:10.1016/j.entcs.2006.01.027

Cited by 9 publications

(7 citation statements)

References 5 publications

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“…Analog hardware description languages, use of MATLAB/Simulink for modeling and modeling of mixed-signal SoC designs are described in [3][4][5][6][7]. There has also been research on formal verification of mixed-signal circuits based on property checking [8,9]. However, it is difficult to check the dynamic behavior of mixed-signal/RF systems using formal checking methods.…”

Section: State Of the Artmentioning

confidence: 99%

Validation signature testing

Chatterjee

Deyati

Muldrey

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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Due to the use of scaled technologies, high levels of integration and high speeds of today's mixed-signal SoCs, the problem of validating correct operation of the SoC under electrical bugs and that of debugging yield loss due to unmodeled multi-dimensional variability effects is extremely challenging. Precise simulation of all electrical aspects of the design including the interfaces between digital and analog circuitry, coupling across power and ground planes, crosstalk, etc., across all process corners is very hard to achieve in a practical sense. The problem is expected to get worse as analog/mixed-signal/RF devices scale beyond the 45nm node and are more tightly integrated with digital systems than at present. In this context, a post-silicon validation methodology for analog/mixed-signal/RF SoCs is proposed that relies on the use of special stimulus designed to expose differences between observed DUT behavior and its predictive model. The corresponding error signature is then used to identify the likely "type" of electrical bug and its location in the design using nonlinear optimization algorithms. Results of trial experiments on RF devices are presented.

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Section: State Of the Artmentioning

confidence: 99%

Validation signature testing

Chatterjee

Deyati

Muldrey

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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“…In [13], the authors developed a bounded model checking tool (Property-Checker ) for the verification of the quasi-static behavior of AMS designs.…”

Section: Relevant Workmentioning

confidence: 99%

Formal verification of analog and mixed signal designs: A survey

Zaki

Tahar

Bois

2008

Microelectronics Journal

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Analog and Mixed Signal (AMS) designs are an important part of embedded systems that link digital designs to the analog world. Due to challenges associated with its verification process, AMS designs require a considerable portion of the total design cycle time. In contrast to digital designs, the verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches.

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“…By providing the possibility of creating parameterized macro functions involving a macro preprocessor, specification code can be sourced out to macro libraries allowing encapsulation and reuse of specification code. The application of ASL specifications and algorithms is not restricted to state space models generated with the approach described in the preceding section, so it can be adopted to other finite state machine-based modeling approaches like [11].…”

Section: Analog Specification Languagementioning

confidence: 99%