Automatic Quantification of Cache Side-Channels

Abstract

Abstract. The latency gap between caches and main memory has been successfully exploited for recovering sensitive input to programs, such as cryptographic keys from implementation of AES and RSA. So far, there are no practical general-purpose countermeasures against this threat. In this paper we propose a novel method for automatically deriving upper bounds on the amount of information about the input that an adversary can extract from a program by observing the CPU's cache behavior. At the heart of our approach is a novel technique for efficient counting of concretizations of abstract cache states that enables us to connect state-of-the-art techniques for static cache analysis and quantitative information-flow. We implement our counting procedure on top of the AbsInt TimingExplorer, one of the most advanced engines for static cache analysis. We use our tool to perform a case study where we derive upper bounds on the cache leakage of a 128-bit AES executable on an ARM processor with a realistic cache configuration. We also analyze this implementation with a commonly suggested (but until now heuristic) countermeasure applied, obtaining a formal account of the corresponding increase in security.

Leakage Resilience against Concurrent Cache Attacks

“…Observing a cache state models leakage about accesses to memory space that is shared between victim and adversary, as in [13]. For modeling disjoint memory spaces, we consider observations that only reveal how many memory blocks are loaded in each cache set [17].…”

“…CacheAudit makes use of the fact that one can obtain upper bounds for the information leaked through the cache by abstract interpretation and model counting [17,18].…”

Maximizing entropy over Markov processes

“…Among the other measures vulnerability has been shown by Smith to have interesting qualities when considering a single attack by an attacker with no prior information about the secret [14], and Köpf et al show how to use probabilistic measures to quantify the security of side channels [15,16]. Providentially, for deterministic protocols the orderings induced by all measures of insecurity coincide [7,17], showing the robustness of the approach.…”

A Library for Removing Cache-Based Attacks in Concurrent Information Flow Systems

“…Allowing some information leakage, Kopft et al [17] combines abstract interpretation and quantitative information-flow to analyze leakage bounds for cache attacks. Kim et al [15] propose StealthMem, a system level protection against cache attacks.…”