Automatic Replacement of Flip-Flops by Latches in ASICs

Chinnery, David; Keutzer, Kurt; Sanghavi, J.; Killian, Earl; Sheth, Kaushik

doi:10.1007/0-306-47823-4_7

Cited by 7 publications

(5 citation statements)

References 6 publications

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“…The selected group of flip-flops is subsequently converted into latches and retimed. Standard synthesis tools do not support latch retiming, however their ability to retime flip-flops can be leveraged with a previously established procedure [21], [26]. First, each latch of the original flip-flop is replaced by a flipflop, depicted in Fig.…”

Section: Insertion Flowmentioning

confidence: 99%

Latch-Based Logic Locking

Sweeney

Zackriya

Pagliarini

et al. 2020

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

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Globalization of IC manufacturing has led to increased security concerns, notably IP theft. Several logic locking techniques have been developed for protecting designs, but they typically display very large overhead, and are generally susceptible to deciphering attacks. In this paper, we propose latch-based logic locking, which manipulates both the flow of data and logic in the design. This method converts an interconnected subset of existing flip-flops to pairs of latches with programmable phase. In tandem, decoy latches and logic are added, inhibiting an attacker from determining the actual design functionality. To validate this technique, we developed and verified a locking insertion flow, analyzed PPA and ATPG overhead on benchmark circuits and industry cores, extended existing attacks to account for the technique, and taped out a demonstration chip. Importantly, we show that the design overhead with this approach is significantly less than with previous logic locking schemes, while resisting model checker-based, oracle-driven attacks. With minimal delay overhead, large numbers of decoy latches can be added, cheaply increasing attack resistance.

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Section: Insertion Flowmentioning

confidence: 99%

Latch-Based Logic Locking

Sweeney

Zackriya

Pagliarini

et al. 2020

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

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“…Efficient implementations of EBs can be derived using levelsensitive latches, either in asynchronous designs [34], [59] or in synchronous designs [31], [52]. These implementations are based on the observation that each edge-triggered flip-flop is composed of two level-sensitive latches (master and slave) [27] that can potentially store different data if they can be controlled independently. The resulting approach is shown in Fig.…”

Section: A Latch-based Implementations Of Ebsmentioning

confidence: 99%

“…In case of synchronous elastic circuits, a conventional twophase clocking scheme for latch-based circuits can be used. When the logic between pairs of latches is unbalanced, time borrowing is typically used to compensate for the difference of delays between adjacent stages [27]. This situation occurs when the flip-flops are split into pairs of master/slave latches, without any logic between master and slave.…”

Section: B Timingmentioning

confidence: 99%

Elastic Circuits

Carmona

Cortadella

Kishinevsky

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous design. Elasticity can be implemented both synchronously and asynchronously, although it was traditionally more often associated with asynchronous circuits. This paper shows that synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques. Thus, choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.

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“…A disadvantage of latches, however, is that they are subject to races that violate hold time constraints (hold violation), because transparency allows short-path delay to pass through adjacent function blocks, different from timing analysis in FFbased design. Two-phase non-overlapping clocking scheme was used to fix the hold violation, which in turn increases the design cost to manage two clocks [1].…”

Section: Introductionmentioning

confidence: 99%

Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis

Inoue

Kaneko

2012

Proceedings of the Great Lakes Symposium on VLSI

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Flip-flop (FF)/latch-based design has advantages on such as area and power compared to single register-type design (only FFs or latches). Considering FF/latch-based design at high-level synthesis is necessary, because resource binding process significantly affects the quality of resulting circuits. A major downside of FF/latch-based design is the increase in resources (functional units and registers) due to the modification of the lifetimes of operations and data. Therefore, as a first step, this paper addresses the datapath design problem in which resource binding and register-type selection are simultaneously optimized for resource optimization. An efficient comprehensive framework is presented, which has flexibility to incorporate other design objectives. Experiments show that the proposed approach can generate resource-efficient FF/latch-based datapaths.

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Automatic Replacement of Flip-Flops by Latches in ASICs

Cited by 7 publications

References 6 publications

Latch-Based Logic Locking

Latch-Based Logic Locking

Elastic Circuits

Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis

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