Automatic Software Hardware Co-Design for Reconfigurable Computing Systems

Saha, Proshanta

doi:10.1109/fpl.2007.4380702

Cited by 11 publications

(7 citation statements)

References 8 publications

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“…Therefore, overall can provide efficient system-level mechanisms targeting both development productivity impact of innovations in Translation fixed and reconfigurable computing structures facilitating phase may be modest as compared to impact of Formulation abstraction of underlying hardware details from the user [20]. and Design innovations.…”

Section: System-level Parallel Languagesmentioning

confidence: 99%

Strategic Challenges for Application Development Productivity in Reconfigurable Computing

Merchant¹,

Holland²,

Reardon³

et al. 2008

2008 IEEE National Aerospace and Electronics Conference

Self Cite

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Performance and versatility requirements arising infuse into mainstream computing systems resulting in a from escalating fabrication costs and design complexities are technological convergence and reformation. Figure 1 shows making reconfigurable computing technologies increasingly the landscape of evolving device architectures. In this paper advantageous on the roadmap towards many-core technologies. we do not distinguish between multi-core and many-core This reformation in device architectures is necessitating a devices and use the notation MC to refer to them collectively. critical reformation in application design methods to bridge the The two primary classes of MC architectures technology are widening semantic gap between design productivity and fixed MC (FMC) devices and reconfigurable MC (RMC) execution efficiency. This paper explores the strategic devices. FMC devices have fixed hardware structure that challenges in FPGA design methodologies and evaluates cannot be changed after fabrication, whereas RMC devices potential solutions and their impact on future DoD applications can change hardware structure post-fabrication to adapt to and users. A new research initiative, Strategic Infrastructure for Reconfigurable Computing Applications (SIRCA), has also cf re quiRemes Depe on the types been proposed as a potential new DARPA program to address cores in FMC and RMC devices these can be further divided the FPGA productivity problem. in homogeneous and heterogeneous devices. Early indicators of this convergence trend can be seen in vendor roadmaps and upcoming device architectures such as the Intel tera-scale I. ARCHITECTURE REFORMATION research chip (homogeneous FMC) [3], Cell processor Unsustainable thermal and power overheads have (heterogeneous FMC) [4], Tile-64 processor (homogeneous saturated achievable clock frequencies in modern processors, RMC) [2], Monarch (heterogeneous RMC) [5], and FPGA ending the performance growth relying on instruction-level (heterogeneous RMC) [1]. parallelism and higher clock frequencies. The continued quest for higher performance has started a new trend focusing on thread-and task-level parallelism, leading to the emergence of homogeneous and heterogeneous multi-/many-core computing structures. As the number of cores on a chip increases, relative performance benefits from thread-level parallelism will diminish as per Amdahl's Law, necessitating performance gains through other types of parallelism that can be achieved mainly by heterogeneous, many-core computing structures. Furthermore, increasingly high fabrication costs will encourage use of reconfigurable computing (RC) structures ranging from gate-level, reconfigurable devices such as FPGAs [1] to interconnect-level, reconfigurable devices such as Tile-64 processor [2] to increase versatility and therefore market size. Thus, diverse design paradigms and architectures from parallel and custom computing systems will eventually Figure 1. Landscape of future computing devices This material is based on research sponsored by D...

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Section: System-level Parallel Languagesmentioning

confidence: 99%

Strategic Challenges for Application Development Productivity in Reconfigurable Computing

Merchant¹,

Holland²,

Reardon³

et al. 2008

2008 IEEE National Aerospace and Electronics Conference

Self Cite

View full text Add to dashboard Cite

show abstract

“…However, even if a single PE could accommodate multiple tasks, the tasks were executed in a sequential way. In Saha [2007], an automatic HW/SW co-design approach on RCs was proposed. The proposed ReCoS algorithm partitioned a program into hardware tasks and software tasks and co-scheduled the tasks on their respective PEs.…”

Section: Related Workmentioning

confidence: 99%

Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing

Huang

Narayana

Simmler

et al. 2010

ACM Trans. Reconfigurable Technol. Syst.

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High-performance reconfigurable computing involves acceleration of significant portions of an application using reconfigurable hardware. When the hardware tasks of an application cannot simultaneously fit in an FPGA, the task graph needs to be partitioned and scheduled into multiple FPGA configurations, in a way that minimizes the total execution time. This article proposes the Reduced Data Movement Scheduling (RDMS) algorithm that aims to improve the overall performance of hardware tasks by taking into account the reconfiguration time, data dependency between tasks, intertask communication as well as task resource utilization. The proposed algorithm uses the dynamic programming method. A mathematical analysis of the algorithm shows that the execution time would at most exceed the optimal solution by a factor of around 1.6, in the worst-case. Simulations on randomly generated task graphs indicate that RDMS algorithm can reduce interconfiguration communication time by 11% and 44% respectively, compared with two other approaches that consider data dependency and hardware resource utilization only. The practicality, as well as efficiency of the proposed algorithm over other approaches, is demonstrated by simulating a task graph from a real-life application -N-body simulation -along with constraints for bandwidth and FPGA parameters from existing high-performance reconfigurable computers. Experiments on SRC-6 are carried out to validate the approach.

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“…However, even if a single PE could accommodate multiple tasks, the tasks were executed in a sequential way. In [10], an automatic HW/SW co-design approach on RCs was proposed. The proposed ReCoS algorithm partitioned a program into hardware tasks and software tasks and coscheduled the tasks on their respective PEs.…”

Section: Related Workmentioning

confidence: 99%

RDMS: A hardware task scheduling algorithm for Reconfigurable Computing

Huang

Simmler

Serres

et al. 2009

2009 IEEE International Symposium on Parallel &Amp; Distributed Processing

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Reconfigurable Computers (RC) can provide significant performance improvement for domain applications. However, wide acceptance of today's RCs among domain scientist is hindered by the complexity of design tools and the required hardware design experience. Recent developments in HW/SW co-design methodologies for these systems provide the ease of use, but they are not comparable in performance to manual co-design. This paper aims at improving the overall performance of hardware tasks assigned to FPGA devices by minimizing both the communication overhead and configuration overhead, which are introduced by using FPGA devices. The proposed Reduced Data Movement Scheduling (RDMS) algorithm takes data dependency among tasks, hardware task resource utilization, and inter-task communication into account during the scheduling process and adopts a dynamic programming approach to reduce the communication between µP and FPGA co-processor and the number of FPGA configurations to a minimum. Compared to two other approaches that consider data dependency and hardware resource utilization only, RDMS algorithm can reduce inter-configuration communication time by 11% and 44% respectively based on simulation using randomly generated data flow graphs. The implementation of RDMS on a real-life application, N-body simulation, verifies the efficiency of RDMS algorithm against other approaches.

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Automatic Software Hardware Co-Design for Reconfigurable Computing Systems

Cited by 11 publications

References 8 publications

Strategic Challenges for Application Development Productivity in Reconfigurable Computing

Strategic Challenges for Application Development Productivity in Reconfigurable Computing

Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing

RDMS: A hardware task scheduling algorithm for Reconfigurable Computing

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