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Reconfigurable Computers (RC) can provide significant performance improvement for domain applications. However, wide acceptance of today's RCs among domain scientist is hindered by the complexity of design tools and the required hardware design experience. Recent developments in hardware/software co-design methodologies for these systems provide the ease of use, but they are not comparable in performance to manual co-design. This paper aims at improving the overall performance of hardware tasks assigned to FPGA. Particularly the analysis of inter-task communication as well as data dependencies among tasks are used to reduce the number of configurations and to minimize the communication overhead and task processing time. This work leverages algorithms developed in the RC and Reconfigurable Hardware (RH) domains to address efficient use of hardware resources to propose two algorithms, Weight-Based Scheduling (WBS) and Highest Priority First-Next Fit (HPF-NF). However, traditional resource based scheduling alone is not sufficient to reduce the performance bottleneck, therefore a comprehensive algorithm is necessary. The Reduced Data Movement Scheduling (RDMS) algorithm is proposed to address dependency analysis and inter-task communication optimizations. Simulation shows that compared to WBS and HPF-NF, RDMS is able to reduce the amount of FPGA configurations to schedule random generated graphs with heavy weight nodes by 30% and 11% respectively. Additionally, the proof-of-concept implementation of a complex 13-node example task graph on the SGI RC100 reconfigurable computer shows that RDMS is not only able to trim down the amount of necessary configurations from 6 to 4 but also to reduce communication overhead by 48% and the hardware processing time by 33%. * One instantiation of a FPGA configuration is denoted to the process of loading the corresponding bitstream into the device, configuring it, executing the tasks in the configuration, and then releasing the device.

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in various capacities. The heterogeneous computing community has introduced several algorithms to handle the Current work on automatic task partitioning and scheduling scheduling of heterogeneous processors in a distributed for reconfigurable computing (RC) systems strictly computing environment [11][12][13]. The HC execution addresses the FPGA hardware, and does not take advantage model however assumes that a given task can be executed of the synergy between the microprocessor and the FPGA. on any available processor. Efforts on partitioning between ptP and the FPGA are a The embedded computing community tackles the issue of manual and laborious effort, as a formal methodology for scheduling in a heterogeneous environment consisting of automatic hardware-software partitioning has not been fixed logic devices such as ASIC and/or special purpose established. Related fields such as heterogeneous processors with the assumption that each task of a program computing (HC) and embedded computing (EC) have an can only execute on a given type of processor extensive body of work for scheduling for heterogeneous [14][15][16][17][18][19]. processors. Unlike the HC scheduling algorithms, the EC For the purpose of distinguishing the two classes of algorithms take into account the differences in development in RC, from here forth techniques that target computational capabilities of each processing element. In only the FPGA will be called reconfigurable hardware (RH)this work, we adapt EC scheduling algorithms for RC algorithms and techniques that target both the FPGA and systems, and show how simply adapting the algorithms the ptP will continue to be referred to as RC systems alone is not sufficient to take advantage of the algorithms. Co-scheduling for RC systems presents reconfigurable hardware. We introduce new heuristic requirements to scheduling, to the best of our knowledge, algorithms based on EC scheduling algorithms and show that have not been addressed before. This paper presents that they provide up to an order of magnitude improvement the co-scheduling requirements of an RC system, and in scheduling and execution times.presents how the rich body of work presented in the EC community can be extended to hardware-software co-

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