Portable library development for reconfigurable computing systems: A case study

Saha, Proshanta; El-Araby, Esam; Huang, Miaoqing; Taher, Mohamed; López-Buedo, Sergio; El‐Ghazawi, Tarek; Shu, Chang; Gaj, Kris; Michalski, Alan; Buell, Duncan A.

doi:10.1016/j.parco.2008.03.005

Cited by 8 publications

(5 citation statements)

References 13 publications

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“…These systems are expensive and use proprietary core services, i.e. software APIs and hardware wrappers, to access the accelerator resources [14]. Some of these systems like those built by Maxeler Technologies [11] even use an own, proprietary hardware description language.…”

Section: Related Workmentioning

confidence: 99%

“…In general, despite a lot of research in the area of reconfigurable computing [1], there are only a few publications on portable and scalable FPGA designs [14,25,26]. They also suggest implementations with varying degrees of parallelism, but do not present a method for automatically determining the hardware parameters as in our framework.…”

Section: Related Workmentioning

confidence: 99%

“…For the user logic, we impose VHDL implementation rules similar to those described in [14]. I.e., no proprietary components can be directly instantiated and no placement constraints are allowed.…”

Section: Hardware Implementation Rulesmentioning

confidence: 99%

See 2 more Smart Citations

SAccO: An implementation platform for scalable FPGA accelerators

Weinhardt

Lang

Thiesing

et al. 2015

Microprocessors and Microsystems

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

SAccO: An implementation platform for scalable FPGA accelerators

Weinhardt

Lang

Thiesing

et al. 2015

Microprocessors and Microsystems

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“…The application is generally decomposed into elementary units of optimized description and synchronized functioning [18]. A new high-level language, called Handel-C, appeared recently [2,8,11,17,[19][20][21][22][23]. Handel-C is based on the conventional ISO-C language and allows the software design of hardware systems.…”

Section: Architectural Models At the Filter Levelmentioning

confidence: 99%

Design and implementation of optimized architecture for computing the 2D‐DWT for JPEG2000 compression

Souani

Gazzah

Besbes

2009

Circuit Theory & Apps

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SUMMARYTo obtain an effective and efficient system, a multitude of architectural solutions must be assessed and their performances compared. Design and evaluation of several hardware architectures require enormous time for their development and the evaluation. In this paper, an exploration of possible architectures for the 2D-discrete wavelet transform (DWT) is accomplished. Particularly, filters used by the standard JPEG2000 are studied: the lossy 9/7 and the lossless 5/3 filters. The designs have been coded with high description level using Handel-C language and the target hardware is Xilinx FPGA of the Virtex-4 family. It is known that the technique of in-place calculation of the 2D-DWT by lifting scheme allows saving space memory, but the problem is that the computed coefficients are not stored in consecutive addresses, and a system for address decoding becomes necessary. The address decoding must be made at every new decomposition level. We propose then a new simple and efficient technique that allows storing the calculated coefficients in a homogeneous space memory and in consecutive addresses. No additional memory or address decoding is necessary. Finally, the designed system allows a rather high throughput and optimized number of hardware resources.

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“…little hardware knowledge to program for the systems [1]. (2) The introduction of hardware libraries in [2] and efforts by [3], [4] and others have made it possible to efficiently utilize the FPGA without significant hardware experience. However, both approaches still relied heavily on the user's hardware knowledge to achieve high performance.…”

Section: Introductionmentioning

confidence: 99%

Hardware task scheduling optimizations for reconfigurable computing

Huang

Simmler

Saha

et al. 2008

2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications

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Reconfigurable Computers (RC) can provide significant performance improvement for domain applications. However, wide acceptance of today's RCs among domain scientist is hindered by the complexity of design tools and the required hardware design experience. Recent developments in hardware/software co-design methodologies for these systems provide the ease of use, but they are not comparable in performance to manual co-design. This paper aims at improving the overall performance of hardware tasks assigned to FPGA. Particularly the analysis of inter-task communication as well as data dependencies among tasks are used to reduce the number of configurations and to minimize the communication overhead and task processing time. This work leverages algorithms developed in the RC and Reconfigurable Hardware (RH) domains to address efficient use of hardware resources to propose two algorithms, Weight-Based Scheduling (WBS) and Highest Priority First-Next Fit (HPF-NF). However, traditional resource based scheduling alone is not sufficient to reduce the performance bottleneck, therefore a comprehensive algorithm is necessary. The Reduced Data Movement Scheduling (RDMS) algorithm is proposed to address dependency analysis and inter-task communication optimizations. Simulation shows that compared to WBS and HPF-NF, RDMS is able to reduce the amount of FPGA configurations to schedule random generated graphs with heavy weight nodes by 30% and 11% respectively. Additionally, the proof-of-concept implementation of a complex 13-node example task graph on the SGI RC100 reconfigurable computer shows that RDMS is not only able to trim down the amount of necessary configurations from 6 to 4 but also to reduce communication overhead by 48% and the hardware processing time by 33%. * One instantiation of a FPGA configuration is denoted to the process of loading the corresponding bitstream into the device, configuring it, executing the tasks in the configuration, and then releasing the device.

show abstract

Portable library development for reconfigurable computing systems: A case study

Cited by 8 publications

References 13 publications

SAccO: An implementation platform for scalable FPGA accelerators

SAccO: An implementation platform for scalable FPGA accelerators

Design and implementation of optimized architecture for computing the 2D‐DWT for JPEG2000 compression

Hardware task scheduling optimizations for reconfigurable computing

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