Automatic synthesis of CMOS RF front-ends

Tulunay, G.; Balkir, S.

doi:10.1109/iscas.2006.1692663

Cited by 9 publications

(10 citation statements)

References 9 publications

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“…On the other hand, equation-based methods [5][6][7] are faster, but are dependent on the accuracy of the models used. To overcome the disadvantages in some extent, advanced methods using both of equation-based and simulationbased approaches [8][9][10] have been also suggested.…”

Section: Introductionmentioning

confidence: 99%

An Analytical Approach for Fast Automatic Sizing of Narrow-Band RF CMOS LNAs

Choi

2012

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We introduce a fast automatic sizing algorithm for a single-ended narrow-band CMOS cascode LNA adopting an inductive source degeneration based on an analytical approach without any optimization procedure. Analytical expressions for principle parameters are derived based on an ac equivalent circuit. Based on the analytical expressions and the power-constrained noise optimization criteria, the automatic sizing algorithm is developed. The algorithm is coded using Matlab, which is shown capable of providing a set of design variable values within seconds. One-time Spectre simulations assuming usage of a commercial 90 nm CMOS process are performed to confirm that the algorithm can provide the aimed first-cut design with a reasonable accuracy for the frequency ranging up to 5 GHz. This work shows one way how accurate automatic synthesis can be done in an analytical approach.

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Section: Introductionmentioning

confidence: 99%

An Analytical Approach for Fast Automatic Sizing of Narrow-Band RF CMOS LNAs

Choi

2012

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“…2: for any specified target circuit performance, the P-Cell first chooses the optimal LNA topology and then calculates the optimal values for each circuit component. In other words, the P-Cell determines the circuit parameters such as transistor size, bias condition and passive value automatically for any given circuit performance specifications, which is a reverse-direction approach compared with the commonly-used approach in the synthesis [1][2][3] (calculating the circuit performance metrics from chosen circuit parameters).…”

Section: P-cell Building Approachmentioning

confidence: 99%

“…Available LNA design automation is mainly based on circuit synthesis [1][2][3]. Starting at some initial circuit component values such as transistor size, bias condition and passive values, the circuit performance metrics are calculated and then a cost function is evaluated.…”

Section: Introductionmentioning

confidence: 99%

A multi-step P-cell for LNA design automation

Cheng

Annema

Nauta

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-This paper presents a novel way to efficiently implement parametric cells (P-cells). A narrow-band LNA is used as demonstration vehicle. In the P-cell, circuit parameters such as transistor size, bias condition and passive values are determined automatically for any given reachable target performance. To achieve both high accuracy and relatively high speed, a new iterative stepped approach is used with respect to speed and accuracy, starting with moderate-accuracy and fast optimization that yields the starting point for the next higheraccuracy and slower optimization step. The presented approach can be extended to other types of circuits.

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“…However, this further complicates the expression for determination of L s , and hence the model in Fig. 2 a has been followed by many authors [1,2,3,4,5,7]. Further, in all the models of Fig.…”

Section: Introductionmentioning

confidence: 99%

“…1, a simple small signal transistor model shown in Fig. 2 a has been made use of [1,2,3]. This model includes the gate to source capacitor and a dependent current source controlled by the voltage between gate to source terminals, but other capacitance and transconductance effects are not included.…”

Section: Introductionmentioning

confidence: 99%

Design space exploration of inductive degenerated Common - Source Low Noise Amplifiers (CS-LNA)

Thangavelu

2013

IEICE Electron. Express

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Abstract:The inductive degenerated Common Source (CS) Low Noise Amplifier (LNA) is one of the widely used topology for realizing narrow band Radio Frequency (RF) CMOS LNAs. Though this scheme has been in use for a long time, realizing an optimum design still remains a challenging task. The present paper reports a simple and direct design space exploration procedure for the inductive degenerated CS LNA. The procedure first involves the use of a circuit simulator (Cadence Spectre) to generate a Look Up Table of small signal parameters. These are then used in a numerical simulator (MATLAB) to explore the entire design space by computing the various performance parameters and arrive at the final optimal designs. The predicted performances of the optimum designs were then verified using UMC 180 nm CMOS process parameters in Cadence Spectre. Completing all the computations on a typical low end desktop system within about an hour, the results presented indicate that one can search a design space of nearly fourteen million design candidates and arrive at an optimum of one's choice.

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Automatic synthesis of CMOS RF front-ends

Cited by 9 publications

References 9 publications

An Analytical Approach for Fast Automatic Sizing of Narrow-Band RF CMOS LNAs

An Analytical Approach for Fast Automatic Sizing of Narrow-Band RF CMOS LNAs

A multi-step P-cell for LNA design automation

Design space exploration of inductive degenerated Common - Source Low Noise Amplifiers (CS-LNA)

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