Automatically characterizing large scale program behavior

Sherwood, Timothy; PerelmanErez,; Hamerly, Greg; CalderBrad,

doi:10.1145/635508.605403

Cited by 423 publications

(674 citation statements)

References 25 publications

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“…Since network bandwidth is a bottleneck in the CMP, we also show CMP results with twice as much bandwidth. As a workload, we employ SPEC2k programs executed for 100 million instruction windows identified by the Simpoint toolkit [33]. The composition of programs in our multi-programmed CMP workload is described in the next sub-section.…”

Section: Methodsmentioning

confidence: 99%

Interconnect design considerations for large NUCA caches

MuralimanoharNaveen

BalasubramonianRajeev

2007

SIGARCH Comput. Archit. News

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The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposals advocate splitting the cache into a large number of banks and employing a network-on-chip (NoC) to allow fast access to nearby banks (referred to as Non-Uniform Cache Architectures -NUCA). Most studies on NUCA organizations have assumed a generic NoC and focused on logical policies for cache block placement, movement, and search. Since wire/router delay and power are major limiting factors in modern processors, this work focuses on interconnect design and its influence on NUCA performance and power. We extend the widely-used CACTI cache modeling tool to take network design parameters into account. With these overheads appropriately accounted for, the optimal cache organization is typically very different from that assumed in prior NUCA studies. To alleviate the interconnect delay bottleneck, we propose novel cache access optimizations that introduce heterogeneity within the inter-bank network. The careful consideration of interconnect choices for a large cache results in a 51% performance improvement over a baseline generic NoC and the introduction of heterogeneity within the network yields an additional 11-15% performance improvement.

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Section: Methodsmentioning

confidence: 99%

Interconnect design considerations for large NUCA caches

MuralimanoharNaveen

BalasubramonianRajeev

2007

SIGARCH Comput. Archit. News

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“…We use the Simpoint tool [23] to obtain a representative slice for each benchmark (with full reference input set) and each benchmark is fast-forwarded to its representative point before detailed simulation takes place. The simulations continue until one benchmark within a workload finishes the execution of the representative interval of 250M instructions.…”

Section: Workloads and System Configurationsmentioning

confidence: 99%

Thermal Design Space Exploration of 3D Die Stacked Multi-core Processors Using Geospatial-Based Predictive Models

Cho

Zhang

2009

Computer Performance Evaluation and Benchmarking

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Abstract. -This paper presents novel 2D geospatial-based predictive models for exploring the complex thermal spatial behavior of three-dimensional (3D) die stacked multi-core processors at the early design stage. Unlike other analytical techniques, our predictive models can forecast the location, size and temperature of thermal hotspots. We evaluate the efficiency of using the models for predicting within-die and cross-dies thermal spatial characteristics of 3D multi-core architectures with widely varied design choices (e.g. microarchitecture, floor-plan and packaging). Our results show the models achieve high accuracy while maintaining low complexity and computation overhead.

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“…Being aware of this large-scale timevarying behavior is key to understanding the behavior of the program as a whole. Phase behavior can be exploited for various purposes, ranging from performance modeling [1], compiler optimizations [2], hardware adaptation [3][4] [5][6] [7], etc. For example in phase-based hardware adaptation, if we know that particular parts of the processor are unused during some program phase, we can turn off those parts during that phase resulting in a reduced energy consumption without affecting overall performance.…”

Section: Introductionmentioning

confidence: 99%

“…One way of identifying phases is to divide the complete program execution into fixed-length instruction intervals and to group instruction intervals based on the code that is being executed during those intervals-this is often referred to as the temporal approach [1]. This means that intervals that execute the same code will be grouped together in what will be called a phase.…”

Section: Introductionmentioning

confidence: 99%

A Detailed Study on Phase Predictors

Vandeputte

Eeckhout

Bosschere

2005

Euro-Par 2005 Parallel Processing

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Abstract. Most programs are repetitive, meaning that some parts of a program are executed more than once. As a result, a number of phases can be extracted in which each phase exhibits similar behavior. These phases can then be exploited for various purposes such as hardware adaptation for energy efficiency. Temporal phase classification schemes divide the execution of a program into consecutive (fixed-length) intervals. Intervals showing similar behavior are grouped into a phase. When a temporal scheme is used in an on-line system, phase predictors are necessary to predict when the next phase transition will occur and what the next phase will be. In this paper, we analyze and compare a number of existing state-of-the-art phase predictors using the SPEC CPU2000 benchmarks. The design space we explore is huge. We conclude that the 2-level burst predictor with confidence and conditional update is today's most accurate phase predictor within reasonable hardware budgets.

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Automatically characterizing large scale program behavior

Cited by 423 publications

References 25 publications

Interconnect design considerations for large NUCA caches

Interconnect design considerations for large NUCA caches

Thermal Design Space Exploration of 3D Die Stacked Multi-core Processors Using Geospatial-Based Predictive Models

A Detailed Study on Phase Predictors

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