Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology

Abstract

Traditionalregister-transfer level design methodologies for systems-on-chip are failing to keep up with the growing complexity of embedded applications and architectures. A well-known solution is to raise the level of design abstraction by using system-level methodologies. The refinement from system-level specifications to concrete implementations is an essential step in a system-level design methodology. This article presents a novel methodology for the refinement from transaction-level communications to pin-and cycleaccurate protocols as well as the generation of synthesizable hardware from system-level specifications. Automatic communication refinement and hardware synthesis were successfully applied to a rover guiding system. Hand-coded and automatically generated register-transfer level modules of the rover are compared. Results show that a hardware/software implementation of the guiding system using generated register-transfer level modules has overheads of less than one percent in latency and hardware area when compared to an implementation using hand-coded modules.

Customer application protocol for data transfer between embedded processor and microcontroller systems

“…For exchanging data between the two systems, two points need to be considered. The first point is that the microblaze uses big-endian bit-reversed data format [17] while the microcontroller system uses little-endian format to represent the data, also the data transmission in CAP protocol was performed in little-endian mode. Figure 2 shows the big-endian data format representation and Figure 3 shows the location of the data bytes on memory in each mode.…”

Synthesis of optimized hardware transactors from abstract communication specifications

“…Hatami et al [11] and Bombieri et al [2] propose a similar approach but with the interfaces written in SystemC TLM-2.0. Moss et al [16] utilize communication refinement and HLS tools to generate a data slicing transactor that realizes pin-level interfaces down to a final RTL bus adapter. Beyond academia, several commercial HLS tools [4,6] have started to integrate similar capabilities of synthesizing interface functions written in TLM form.…”