Avoiding divergent oscillation of cascode GaN device under high current turn-off condition

Abstract

Cascode structure is widely used for high voltage normally-on GaN devices. However, the capacitance mismatch between the high voltage GaN device and the low voltage normally-off Si MOSFET may induce several undesired features, such as Si MOSFET reaches avalanche during turn-off, and high voltage GaN device loses ZVS turn-on condition internally during soft-switching turn-on process in every switching cycle. This paper presents another issue associated with the capacitance mismatch in the cascode GaN devices. Divergent oscillation could occur at high current turn-off condition, and eventually destroy the device. The intrinsic reason of this phenomenon is analyzed in detail in this paper. A simple solution is proposed by adding an additional capacitor whose position is critical and should be optimized. Experimental results validate the theoretical analysis, and show that the proposed method improves device performance significantly under high current turn-off condition.

Fabrication of All-GaN Integrated MIS-HEMTs with High Threshold Voltage Stability Using Supercritical Technology

“…However, a few issues have been reported that may negate the speed advantage in the GaN plus Si hybrid cascode devices, such as increased parasitic inductance [ 4 ] and mismatch in intrinsic capacitances between the Si and GaN devices [ 5 ]. All-GaN integrated cascode device by replacing the Si MOSFET with a low voltage GaN E-mode device achieved using fluoride ion implantation has proven to be able to address the issues mentioned above and improve the switching speed [ 3 ].…”

Field Plate Designs in All-GaN Cascode Heterojunction Field-Effect Transistors

“…1, was demonstrated with a superior hard switching performance at 200 V compared to the equivalent standalone GaN heterojunction field effect transistor (HFET) [1]. However, further optimization of the integrated cascode is still required to address several known issues from experience in the GaN plus Si hybrid cascode device [4][5][6], which also apply to the integrated cascode structure. First, the mismatch in intrinsic capacitances between the depletion mode (D-mode) and the enhancement mode (E-mode) devices can lead to an increased off-state voltage at the internode of the cascode configuration [4][5].…”

All-GaN-Integrated Cascode Heterojunction Field Effect Transistors

“…This makes cascode devices strong candidates for high power and high frequency switching applications. However, a few issues have been reported that may negate the speed advantage in the GaN plus Si hybrid cascode devices [10][11][12][13]. Firstly, the connections between the Si MOSFET and GaN devices result in increased parasitic inductance, which can cause excessive 'ringing' effects at fast switching speed thus limiting high frequency operation [12][13].…”

“…In addition, due to the mismatch in intrinsic capacitances between the Si and GaN devices and the body diode in the Si MOSFET, the Si device can be driven into avalanche mode causing additional switching energy loss [10]. Moreover, the mismatched capacitances together with the parasitic inductance may cause large oscillations during turn-off under high current operation [11]. Adding an external capacitor between the drain and gate of the Si device was proposed in [10] and [11] to match the capacitance in the hybrid cascode device and prevent avalanche in the Si device, at the expense of additional parasitic inductance and careful designs in the device packaging are required.…”

“…The avalanche in the low voltage device during turn-off can be avoided due to the lack of body diode in the GaN E-mode device. In additional, the parasitic inductance can be minimized by monolithic integration, reducing the oscillation during turn-off operation [11] as well as leading to improved parallel operation [16]. Only a few studies on the integrated cascode structure have been reported and are limited to RF applications [17] and [18].…”