(Ba,Sr)TiO/sub 3/ capacitor technology for Gbit-scale DRAMs

Abstract

Great efforts have been made for the integration of high dielectric constant (Ba,Sr)Ti03 (BST) capacitors into DRAMs. This paper presents the current state of the art in BST capacitor technology for Gbit-scale DRAMs, with emphasis on key technical issues for process integration, including electrode materials, barrier layers, and also BST films themselves. The problems which may remain to be solved are also discussed to realize the goal: a barrier layer on top electrode for back-end processes, reliability of integrated BST capacitors, and further improvement of coverage properties of BST films and cell-plate metals.been achieved so far. On the other hand, in a 3-D stack, the sidewall capacitance increases with increasing the height of patterned stlorage nodes, which gives the scaling of this structure down to Gbit dimensions. These 3-D stack capacitors may be further classed under two types, having tapered and vertical storage nodes. It should be noted that for the 3-D stack with tapered storage nodes, their height is limited by geometrical conditions where the bottom of tapered electrodes would be buried in the small spacing between storage nodes; e.g., for a typical sidewall angle 8=70", the hleight of storage nodes is limited to D10.25 pm in 0.18 pm rule and to DI0.18 pm in 0.13 prn rule (4-Gbit), which in turn requires &,I0.34 nm and t&0.18 MI, respectively Introduction Electrode Materials From the technology perspective, the DRAM cell is rapidly shrinking as shown in Fig. 1, which in turn leads to aggressive scaling of memory cell capacitors while maintaining the storage capacitance therein.The minimum storage capacitance required remains to be C,225 @/cell even for Gbit-scale DRAMs, relying on the sense amplifier sensitivity, data retention time, and soft error immunity. Capacitor technology with high dielectric constant BST films has been developed to meet these requirements [ 1-51, as an alternative to capacitors using conventional dielectric materials such as Si3N4/SiOz and Taz05 which are now being actively studied in combination with HSG for 256-Mbit DRAMs. This paper presents the current state of the art in BST capacitor technology for Gbit-scale DRAMs and DRAM-embedded system LSIs, with emphasis on key technical issues for process integration such as electrode materials, barrier layers, and BST films themselves. The problems which may remain to be solved are also discussed to realize the goal.There are"a few different types of BST capacitor structures: a planar and a three-dimensional (3-0) stack capacitor, as shown in Table 1. The planar stack is scalable to 256-Mbit dimensions at most, as can be seen in Fig. 2, because the capacitance comes only from a planar dielectric layer between the bottom and top electrodes (i.e., storage node and cell plate). The equivalent oxide thickness required for a planar type (D=O) is around b=O.12 nm in 0.18 pm (1-Gbit) rule, which is far from the minimum %=0.24 nm that has The electrodle material for storage nodes is still the number one technical issue, because it g...

Investigation of Embedded Perovskite Nanoparticles for Enhanced Capacitor Permittivities

“…Recent experiments on perovskites accessed the nanoscale region with the growth of nanowires 13,14 and nanoparticles. 15,16 So far, CaTiO 3 has not found its way in the preparation of nanostructured devices. Recent results of strain engineering on typically paraelectric CaTiO 3 show ferrielectric behavior at the grain boundaries 17,18 or ferroelectricity at surfaces.…”

“…15,16 So far, CaTiO 3 has not found its way in the preparation of nanostructured devices. Recent results of strain engineering on typically paraelectric CaTiO 3 show ferrielectric behavior at the grain boundaries 17,18 or ferroelectricity at surfaces. 19 The possibility to control the number and surrounding of grain boundaries can therefore be used for future device applications.…”

“…In this work, we show a detailed study of perovskite nanocrystallites surrounded by an amorphous matrix for the case of sputter deposited CaTiO 3 . Capacitors with those embedded nanocrystallites exhibit an intermediate permittivity of 50 and above between the permittivity of approximately 105 in a fully crystalline layer and 28 for amorphous CaTiO 3 layers.…”

“…20 Pt is a suitable material for epitaxial growth of perovskites 21,22 with a lattice constant comparable to CaTiO 3 . 23 Besides the good lattice match, the selective growth of the nanocrystallites takes advantage of the different surface energies of CaTiO 3 and Pt facets. Consequential differences in crystal formation energy result in a preferential growth of crystalline CaTiO 3 nanocrystallites in [111] direction on top of the underlying Pt ⟨111⟩ surface texture.…”

“…Consequential differences in crystal formation energy result in a preferential growth of crystalline CaTiO 3 nanocrystallites in [111] direction on top of the underlying Pt ⟨111⟩ surface texture. The embedded nanocrystallites further exhibit a surface passivation by the surrounding matrix of amorphous CaTiO 3 . We show that this effect has been used to significantly reduce leakage currents in 10−30 nm thick metal−insulator−metal (MIM) capacitor stacks.…”