Back-bias generator for post-fabrication threshold voltage tuning applications in 22nm FD-SOI process

Süner, Arif; Jain, Navneet; Rashed, M.

doi:10.1109/isqed.2018.8357299

Cited by 7 publications

(5 citation statements)

References 8 publications

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“…Since we are adopting an FDSOI CMOS process, the value of the body to source voltage is not limited by the forward biasing of bulk diodes and in this case V BBP can be set lower than ground and V BBN higher than V DD to maximize the threshold lowering effect due to FBB. In particular, V BBN has been set to 1 V and V BBP to −1.5 V in order to have V TN about equal to |V TP | around 0.25 V. The adopted values are in the range allowed by the technology (which is −3 V to 3 V as reported in [49]) and can be implemented by suitable back bias generators as in [50].…”

Section: Simulation Results and Comparisonmentioning

confidence: 99%

0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

2021

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Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

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Section: Simulation Results and Comparisonmentioning

confidence: 99%

0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

2021

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“…The above-mentioned power nets must be routable independently. This feature is available in almost all recent nanometer CMOS technologies, where adaptive body bias (ABB) and adaptive supply voltage scaling (ASV) are frequently utilized by digital designers to cope with PVT variations and to reduce the spread of maximum operating frequency and power consumption [21]- [29]. In these approaches, specific Body Bias Generators are exploited to provide forward body bias (FBB) or reverse body bias (RBB) for optimizing the speed/power consumption tradeoff.…”

Section: Biasing Approachmentioning

confidence: 99%

“…Once designed, the ABBG can be used as an ordinary reusable standard-cell library element for several SoCs. The full custom design and library implementation of the ABBG can be carried out by the IC manufacturer and the ABBG library distributed together with the standard cell library as happens for body bias generator libraries used for digital circuits [21][22][23][24][25][26][27][28].…”

Section: A Semi-custom Design Flowmentioning

confidence: 99%

A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs

et al. 2022

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“…To cope with these issues, approaches that exploit body biasing of the standard-cells, together with a custom-designed body bias generator, have been proposed in the literature [45,58,59]. However, these solutions require the availability of the body terminals: this is common in modern technologies, where body biasing is exploited to compensate for PVT variations in digital circuits [60,61], but it is not compatible with older technologies often used for analog designs. Moreover, the limited gain of the body input could require control voltages beyond the supply rails to cope with large bias point variations.…”

Section: Introductionmentioning

confidence: 99%

A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow

2023

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In this paper, we propose a novel standard-cell-based OTA architecture based on an improved version of the differential to single-ended converter, previously proposed by the authors, on a novel standard-cell-based basic voltage amplifier block. Due to a replica-bias approach, the basic voltage amplifier exhibits a well-defined output static voltage to allow easy cascadability. Another feature of the basic voltage amplifier is to provide a low output impedance to allow dominant pole compensation at the output of the cascade of several stages. An ultra-low voltage (ULV) standard-cell-based OTA based on the proposed architecture and building blocks has been designed referring to the standard-cell library of a 130-nm CMOS process with a supply voltage of 0.3 V. The layout of the OTA has been implemented by following an automatic layout flow within a commercial tool for the place-and-route of digital circuits. Simulation results have shown a differential gain of 50 dB with a gain–bandwidth product of 10 MHz when driving a 150 pF load capacitance. Good robustness is achieved under PVT variations, in particular for voltage gain, offset voltage, and phase margin. State-of-the-art small signal figures of merit and limited area footprint are key characteristics of the proposed amplifier.

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Back-bias generator for post-fabrication threshold voltage tuning applications in 22nm FD-SOI process

Cited by 7 publications

References 8 publications

0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs

A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow

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