Background Calibration of Multiple Channel Mismatches in Time-Interleaved ADCs

Thi, Yen Hoang; Ta, Van-Thanh; Manh, Duong Quang; Hoang, Van‐Phuc

doi:10.1109/sigtelcom.2019.8696244

Cited by 2 publications

(3 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…SNR increases more than 12 dB, SFDR increases more than 13 dB, and the dynamic performance of the system is close to its sub-ADC dynamic performance. The In Table 1, we compare the method in reference [28] with the method in this paper. After the correction of these two methods, the dynamic performance of the TIADC system used in this paper is very close, which further proves the feasibility of this method in this paper.…”

Section: Discussionmentioning

confidence: 99%

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

Sun

Zhang

et al. 2022

Applied Sciences

View full text Add to dashboard Cite

The performance of analog-to-digital converters (ADCs) has reached a bottleneck due to the limitations of the manufacturing process and testing environment. Time-interleaved ADC (TIADC) technology can increase the sampling rate without changing the resolution. However, channel mismatch severely degrades the dynamic performance of the TIADC system. For the channel mismatch problem of TIADC, most of the current solutions have preconditions, such as eliminating only some kind of error or increasing the complexity of the hardware. A few methods can estimate multiple errors without changing the hardware circuit. To improve the dynamic performance of the TIADC system, on the basis of an in-depth study of the channel mismatch error of TIADC, according to the system identification theory, an identification model is designed to characterize the frequency characteristics of TIADC. Using the system observation data, the transfer function parameters of the system are recursively estimated. By constructing and verifying the identification model of the TIADC system, and then through the frequency domain correction method, a digital compensation filter is established to complete the error correction of the system. The test results of the four-channel TIADC high-speed data acquisition system show that the actual input and output characteristics of the test system are consistent with the nature of the identification model. The four channels of the TIADC system are provided by four sub-channels of two AD9653 chips, and the highest sampling rate of a single channel is 125MSPS. For sinusoidal input signals from 20 MHz to 150 MHz, the sampling system can achieve a signal-to-noise ratio (SNR) above 56.8 dB and spurious free dynamic range (SFDR) above 69.7 dB. The dynamic performance of the sampling system is nearly equivalent to that of its sub-ADC; the feasibility of the model identification method and the effectiveness of error correction are verified in simulation and experiment.

show abstract

Section: Discussionmentioning

confidence: 99%

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

Sun

Zhang

et al. 2022

Applied Sciences

View full text Add to dashboard Cite

show abstract

“…However, the main limitation of this technique is that there is an overlap between the basic function and desired signal when the input signal is single-tone spaced at kM  . Instead of calibrating gain and timing mismatches by combining Hadamard transform and LMS algorithm in [19] or combining modulation matrix and LMS algorithm in [20], in this paper, we calibrate the gain mismatch by calculating the power ratio of the sub-ADC with the reference ADC. Firstly, the offset mismatch is calibrated by taking the average of sub-ADC output samples.…”

Section: Introductionmentioning

confidence: 99%

“…Finally, the timing error is calibrated by using the Hadamard transform and LMS algorithm as in [19]. In [19], [20], a calibration technique was proposed with preliminary results without detail analysis and state ofthe-art comparison.…”

Section: Introductionmentioning

confidence: 99%

All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs

Ta¹,

Hoang²,

Tran³

2019

EAI Endorsed Transactions on Industrial Networks and Intelligen

Self Cite

View full text Add to dashboard Cite

This paper presents a method for all-digital background calibration of multiple channel mismatches including offset, gain and timing mismatches in time-interleaved analog to digital converters (TIADCs). The averaging technique is used to remove the offset mismatch at each channel. The gain mismatch is calibrated by calculating the power ratio of the sub-ADC over the reference ADC. Timing skew is compensated by using Hadamard transform for error correction and least mean squares (LMS) algorithm for estimation of the clock skew. The performance improvement of TIADCs employing these techniques is demonstrated through numerical simulations.

show abstract

Background Calibration of Multiple Channel Mismatches in Time-Interleaved ADCs

Cited by 2 publications

References 11 publications

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

Error Correction Method of TIADC System Based on Parameter Estimation of Identification Model

All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs

Contact Info

Product

Resources

About