Background memory area estimation for multidimensional signal processing systems

Balasa, Florin; Catthoor, Francky; Man, H. De

doi:10.1109/92.386218

Cited by 74 publications

(75 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The inclusion graph is gradually constructed by partitioning analytically the (four) array references using lattice intersections and differences. While the intersection of two non-disjoint lattices is a lattice as well (e.g., [1]), the difference operation is not closed. Denoting A1 ∩ A2 = A3, A1 − A3 and A2 − A3 are also lattices (denoted A4, A5 in Fig.…”

Section: A[k][i]mentioning

confidence: 99%

“…In contrast to the non-scalar methods described so far, the memory estimation technique presented in [1] does not take execution ordering into account, allowing any ordering not prohibited by data dependencies. The estimation technique described in [5] a partially fixed execution ordering.…”

Section: Introductionmentioning

confidence: 99%

“…The estimation technique described in [5] a partially fixed execution ordering. The authors employ a data dependence analysis similar to [1], their major improvement being to add the capability of taking into account available execution ordering information, based mainly on loop interchanges. Different from the previous works which are only approximate methods, this paper presents a non-scalar technique for computing exactly the minimum memory size in multi-dimensional signal processing algorithms, when the specifications are procedural, i.e., the execution ordering is induced by the loop structure and it is thus fixed (like in several previous works [9,10,7]).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Computation of the Minimum Data Storage for Multi-Dimensional Signal Processing

Luican

Zhu

Balasa

2007

2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07

View full text Add to dashboard Cite

-The amount of the data storage in signal processing systems, whose behavior is described by loop-organized algorithmic specifications, has an important impact on the overall energy consumption, chip area, as well as system performance. This paper presents a non-scalar approach for computing the minimum storage requirements in high-level procedural specifications, where the main data structures are multi-dimensional arrays. This methodology uses both algebraic techniques specific to the data-flow analysis used in modern compilers and, also, more recent advances in the theory of polyhedra. In contrast with all the previous works which are only estimation methods, this approach can perform the exact computation of the minimum data storage even for applications with numerous loop nests and complex array references.

show abstract

Section: A[k][i]mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Computation of the Minimum Data Storage for Multi-Dimensional Signal Processing

Luican

Zhu

Balasa

2007

2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07

View full text Add to dashboard Cite

show abstract

“…Studying the impact of parallelism on memory size is important for trading off system performance against area cost. A memory bandwidth analysis is rapidly performed for each level of the graph hierarchy and the Balasa method [3] is currently adapted to our model in order to derive memory size optimization within loop nests.…”

Section: Metric Computations Of the Target Applicationmentioning

confidence: 99%

Design of a multimedia processor based on metrics computation

Amor

Moullec

Diguet³

et al. 2005

Advances in Engineering Software

View full text Add to dashboard Cite

Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-time constraints of those media applications have taxing demands on today's processor performances with low cost, low power and reduced design delay. To satisfy those challenges, a fast and efficient strategy consists in upgrading a low cost general purpose processor core. This approach is based on the personalization of a general RISC processor core according the target multimedia application requirements. Thus, if the extra cost is justified, the general purpose processor GPP core can be enforced with instruction level coprocessors, coarse grain dedicated hardware, ad hoc memories or new GPP cores. In this way the final design solution is tailored to the application requirements. The proposed approach is based on three main steps: the first one is the analysis of the targeted application using efficient metrics. The second step is the selection of the appropriate architecture template according to the first step results and recommendations. The third step is the architecture generation. This approach is experimented using various image and video algorithms showing its feasibility.Key words: design space exploration, media processor, graph-based specification, guidance, metrics 1-IntroductionWe are currently experiencing an important increase in the use of embedded devices with powerful multimedia capabilities such as speech analysis and synthesis, character recognition, video compression, and graphics animation. Due to the various needs of such applications, embedded devices have to handle various data types and various complex tasks under hard real-time constraints. The need for real-time processing of complex algorithms is further accentuated by the increasing interest in other new domains like 3D image. Especially in the domain of embedded systems, the main design constraint is the time to market priority since the availability of a new product at short time even not perfectly optimised is the key point for its commercial success. Another important point in this domain is the opportunity to take advantage of the application characteristics in order to optimize the energy / time / QoS tradeoff. Thus, our strategy is to define a framework that provides a simple and fast analysis tool. The first point is to start with a typical software specification which is automatically transformed into a graph-based internal representation. The idea is to take as an input a standard code without performing any additional effort and to analyze it. Even if the false data dependencies have been eliminated, the resulting hierarchical graph still reflects the designer or standard authors point of view. If such a specification fits with a low cost, low power embedded processor, this is probably the more interesting solution. Secondly, our objective is to extract from the various granularity levels of this specification opportunities of paralleli...

show abstract

“…We will not discuss the detailed process here. 5 Counting heuristic In our current implementation, a heuristic is proposed to deal with the enumeration of the interaction union of images of parameterized polytopes.…”

Section: Statement Level Estimationmentioning

confidence: 99%

Exact memory size estimation for array computations without loop unrolling

Zhao¹,

Malik²

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

View full text Add to dashboard Cite

This paper presents a new algorithm for exact estimation of the minimum memory size required by programs dealing with array computations. Memory size is an important factor a ecting area and power cost of memory units. For programs dealing mostly with array computations, memory cost is a dominant factor in the overall system cost. Thus, exact estimation of memory size required by a program is necessary to provide quantitative information for making high-level design decisions.Based on formulated live v ariables analysis, our algorithm transforms the minimum memory size estimation into an equivalent problem: integer point counting for intersection union of mappings of parameterized polytopes. Then, a heuristics was proposed to solve the counting problem. Experimental results show that the algorithm achieves the exactness traditionally associated with totally-unrolling loops while exploiting the reduced computation complexity b y preserving original loop structure.

show abstract

Background memory area estimation for multidimensional signal processing systems

Cited by 74 publications

References 26 publications

Computation of the Minimum Data Storage for Multi-Dimensional Signal Processing

Computation of the Minimum Data Storage for Multi-Dimensional Signal Processing

Design of a multimedia processor based on metrics computation

Exact memory size estimation for array computations without loop unrolling

Contact Info

Product

Resources

About