No abstract

No abstract

Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing system realizations. In this paper, we present a novel technique { founded on data-ow analysis { which allows to address the problem of background memory size evaluation for a given non-procedural algorithm speci cation, operating on multi-dimensional signals with a ne indices. Most of the target applications are characterized by a huge number of signals, so a new polyhedral data-ow model operating on groups of scalar signals is proposed. These groups are obtained by a novel analytical partitioning technique, allowing to select a desired granularity, depending on the application complexity. The method incorporates a way to trade-o memory size with computational and controller complexity.

Abstract-The traditional way of approaching placement problems in computer-aided design (CAD) tools for analog layout is to explore an extremely large search space of feasible or unfeasible placement configurations, where the cells are moved in the chip plane (being even allowed to overlap in possibly illegal ways) by a stochastic optimizer. This paper presents a novel exploration technique for analog placement operating on a subset of tree representations of the layout-called symmetric-feasible, where the typical presence of an arbitrary number of symmetry groups of devices is directly taken into account during the search of the solution space. The computation times exhibited by this novel approach are significantly better than those of the algorithms using the traditional exploration strategy. This superior efficiency is partly due to the use of segment trees, a data structure introduced by Bentley, mainly used in computational geometry.

The ordered tree (O-tree) representation has recently gained much interest in layout design automation. Different from previous topological representations of non-slicing floorplans, the O-tree representation is simpler, needs linear computation effort to generate a corresponding layout, and exhibits a smaller upper-bound of possible configurations. This paper addresses the problem of handling symmetry constraints in the context of the O-tree representation. This problem arises in analog placement, where symmetry is often used to match layout-induced parasitics and to balance thermal couplings in differential circuits. The good performance of our placement tool dealing with several analog designs taken from industry proves the effectiveness of our technique.