BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks

Abstract

The discrepancy between post-layout and schematic simulation results continues to widen in analog design due in part to the domination of layout parasitics. This paradigm shift is forcing designers to adopt design methodologies that seamlessly integrate layout effects into the standard design flow. Hence, any simulation-based optimization framework should take into account time-consuming postlayout simulation results. This work presents a learning framework that learns to reduce the number of simulations of evolutionarybased combinatorial optimizers, using a DNN that discriminates against generated samples, before running simulations. Using this approach, the discriminator achieves at least two orders of magnitude improvement on sample efficiency for several large circuit examples including an optical link receiver layout.

Today’s computing challenges: opportunities for computer hardware design

“…Conventionally, it was believed that the design space is too huge to fully automate the optimization, even with schematic-only simulation. However, recent progress in deep learning technology enable handling such huge space, so a machine can handle the schematic optimization ( Hakhamaneshi et al, 2019 ). However, as mentioned earlier, the layout automation is almost impossible so the machine must struggle with the layout loop.…”

Building a post-layout simulation performance model with global mapping model fusion technique

“…Formulated as a constrained nonlinear optimization problem, automated analog circuit sizing can be solved using well-developed optimization algorithms [2,3] . Furthermore, closing the design loop to synthesize GDSII files can be further taken into consideration [4] , with generator-based tools, such as Berkeley Analog Generator Two (BAG2) [5] , which can generate clean Design Rule Check (DRC), Layout Versus Schematic (LVS) layouts, and post-layout simulation data.…”

“…Recently, reusing early data for modeling or optimization has become a research trend [4,10,11] . At each stage, the simulated data are collected to verify the circuit designs before proceeding to the next step stage.…”

Cepa

“…Finally, the layout extracted parasitic significantly increases the complexity of the circuit netlist and hence the computation cost. In addition to the time-consuming simulations, the optimization of AMS circuits usually requires tens of thousands of iterations, which tremendously increase the AMS design cost in terms of simulation time [8] [15].…”