Balanced delay trees and combinatorial division in VLSI

Zuras, D.; McAllister, William

doi:10.1109/jssc.1986.1052612

Cited by 31 publications

(7 citation statements)

References 3 publications

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“…Both SPP and MBE techniques are considered in our analysis. Regarding the accumulation tree, the most common architectures are used: 1) Array, 2) Balanced delay, 3) Compressor 4:2, 4) Counter 7:3, 5) Dadda, 6) Dadda with 4:2 compressors, 7) Redundant binary and 8) Wallace [19], [21], [22]. The Array is the simplest way to accumulate the partial products.…”

Section: Exploring the Efficiency Of Partial Product Perforationmentioning

confidence: 99%

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

Zervakis

Tsoumanis

Xydis

et al. 2016

IEEE Trans. VLSI Syst.

117

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Approximate computing has received significant attention as a promising strategy to decrease power consumption of inherently error tolerant applications. In this paper, we focus on hardware level approximation by introducing the Partial Product Perforation technique for designing approximate multiplication circuits. We prove in a mathematically rigorous manner that in partial product perforation the imposed errors are bounded and predictable, depending only on the input distribution. Through extensive experimental evaluation, we apply the partial product perforation method on different multiplier architectures and expose the optimal architecture-perforation configuration pairs for different error constraints. We show that, compared with the respective exact design, the partial product perforation delivers reductions of up to 50% in power consumption, 45% in area and 35% in critical delay. Also, the product perforation method is compared with state-of-the-art approximation techniques, i.e. truncation, Voltage Over-Scaling and logic approximation, showing that it outperforms them in terms of power dissipation and error.

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Section: Exploring the Efficiency Of Partial Product Perforationmentioning

confidence: 99%

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

Zervakis

Tsoumanis

Xydis

et al. 2016

IEEE Trans. VLSI Syst.

117

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“…Balanced delay tree [20]. A tree constructed by connecting progressively larger serial chains of (3, 2) counters.…”

Section: Table 1 Reduction Topology Choice Which Minimizes Latency Acmentioning

confidence: 99%

“…These irregular connections occur because the counter connections are unique for each partial product weight. There have been several different tree structures that have been proposed by Zuras and McAllister [20] and Mou and Jutand [9] that reduce the partial products using more regular interconnections with a slight increase in the number of counter levels over those used by Wallace trees.…”

Section: Introductionmentioning

confidence: 99%

Technology scaling effects on multipliers

Altwaijry

Flynn

1998

IEEE Trans. Comput.

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“…However, in any case, to ensure the accuracy of the synthesis of the output frequency, it is necessary to increase the bit rate and the speed of the synthesizer core, which is built on the basis of a cumulative adder. For this purpose, cumulative adders of complex architecture are used, as shown in the work [3]. However, the use of traditional number systems with sequential transfer between bit positions with increasing synthesized frequency encounters with increasing time of signal propagation and reduction of the maximum possible synthesized frequency.…”

Section: Introductionmentioning

confidence: 99%

Direct Digital Frequency Synthesizer in the Residue Number System

Polikarovskykh¹,

Melnychuk²,

Hula³

et al. 2019

IJC

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The principles of construction and operation of direct digital frequency synthesizers are considered in order to speed up computational operations using Residue Number System. The problems of forming the output signals are considered. The specifics of the implementation of the operation of direct and reverse transformations from positional to non-positional number systems are described. A mathematical model of a synthesizer with a phase accumulator in a Residue Number System is considered. Methods for converting from RNS (Residue Number System) to binary system for problematic operations are considered. The design of a DDS (Direct Digital Synthesizer) with a phase accumulator in a Residue Number System and a converter to an analogue signal form is proposed without the use of slow ROM (Read Only Memory). The article deals with the issues of efficiency of the crystal area of the synthesizer and the reduction of the delays in the formation of the output signal.

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Balanced delay trees and combinatorial division in VLSI

Cited by 31 publications

References 3 publications

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

Technology scaling effects on multipliers

Direct Digital Frequency Synthesizer in the Residue Number System

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