Balanced embedded trace substrate design for warpage control

Evaluation of Residual Stress and Warpage of Device Embedded Substrates with Piezo-Resistive Sensor Silicon Chips

“…The residual stress evaluation of IC packages has generally been conducted using finite element method (FEM) simulation, [11][12][13] nevertheless the FEM simulation is not correct enough to evaluate a large complicated structure exactly and is time-consuming. Consequently, several studies on real measurement of residual stress using a piezo-resistive sensor embedded Si chip have been reported.…”