Ballistic and tunneling GaAs static induction transistors: nano-devices for THz electronics

Nishizawa, Jun Ichi; Płotka, P.; Kurabayashi, Toru

doi:10.1109/ted.2002.1013263

Cited by 32 publications

(15 citation statements)

References 40 publications

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“…The barrier height formed by the completely depleted p + layer is controlled by the applied voltages of the gate and the drain, which indicates the tunnelling and ballistic transport without carrier scattering in the channel. Our group reported a tunnelling and ballistic operation with an estimated electron transit time shorter than 10 −13 s, which is suitable for THz operation [35]. Both heavy doping and a very steep concentration profile are required for high barrier and short channel in this device.…”

Section: Introductionmentioning

confidence: 92%

“…The operation of an ideal SIT has been realized, both with GaAs homojunction and AlGaAs heterojunction gate structures, and transistor operation at room temperature with ballistic electron transport has been achieved [35]. One of the most promising structures for an ideal SIT incorporates a high-k dielectric gate.…”

Section: Sidewall Gaas Tunnel Junction With Tio X Gate Structurementioning

confidence: 99%

“…Structures such as a spin-injection light-emitting diode [25] and a tunnel-injection transit time effect diode (TUNNETT) [26][27][28][29] have also been reported. Tunnel junctions have been used in transistor structures, such as tunnel transistors [30], tunnel-source field-effect transistors (FETs) [31], δ-doped tunnel FETs [32], heterojunction bipolar transistors (HBTs) with a degenerately doped emitter [33], and ideal static-induction transistors (ideal SITs) [34][35][36].…”

Section: Introductionmentioning

confidence: 99%

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Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

Ohno

Oyama

2012

Science and Technology of Advanced Materials

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In this article we review the fundamental properties and applications of sidewall GaAs tunnel junctions. Heavily impurity-doped GaAs epitaxial layers were prepared using molecular layer epitaxy (MLE), in which intermittent injections of precursors in ultrahigh vacuum were applied, and sidewall tunnel junctions were fabricated using a combination of device mesa wet etching of the GaAs MLE layer and low-temperature area-selective regrowth. The fabricated tunnel junctions on the GaAs sidewall with normal mesa orientation showed a record peak current density of 35 000 A cm −2 . They can potentially be used as terahertz devices such as a tunnel injection transit time effect diode or an ideal static induction transistor.

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Section: Introductionmentioning

confidence: 92%

Section: Sidewall Gaas Tunnel Junction With Tio X Gate Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

Ohno

Oyama

2012

Science and Technology of Advanced Materials

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“…We have already developed tunnelling-ballistic GaAs static induction transistors (ISIT) with estimated transit time of electrons shorter than 10 -13 s, suitable for THz operation [1]. Their fabrication process is based on area-selective etching and area-selective lowtemperature epitaxial regrowth of GaAs with molecular layer epitaxy (MLE).…”

Section: Introductionmentioning

confidence: 99%

GaAs area‐selective regrowth with molecular layer epitaxy for integration of low noise and power transistors, and Schottky diodes

Nishizawa¹,

Płotka²,

Kurabayashi

2008

Phys. Status Solidi (c)

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We have developed a GaAs mm‐wave power static induction transistor (SIT) with a regrown source‐drain offset. It was fabricated with low‐temperature, area‐selective molecular layer epitaxial regrowth in a process compatible with that of a low‐noise high‐frequency ideal static induction transistor. The fmax of the power SIT was 111 GHz at gm of 220 mS/mm. These values can be improved with gate engineering. Our method can be used for fabrication of mm‐wave system‐on‐chip wafers including also Schottky barrier diodes. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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“…The quest for understanding nano particle processing methods is a natural consequence of the extensive activities carried out in the last decade that resulted in decreasing the size of electronic devices [1,2]. At present there are many ongoing research activities to explore the most rational and reproducible means of fabricating nano-patterns in a controlled manner [3,4].…”

Section: Introductionmentioning

confidence: 99%

Fabrication of isolated ferroelectric nanostructures

2002

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In this report, we explore the possibilities of the fabrication and characterization of ferroelectric nano-structures by various methods. Techniques include the self-assembly route and direct electron beam lithography. The chemical self-assembly route, which adopted the microemulsionmediated synthesis, appeared to be very encouraging for producing very small monodispersed nano particles and powders, with sizes of 10-60 nm. The possibility to form a two dimensional arrangement of these micro droplets was explored with a suitable choice of the substrate material, and the method of coating. For the patterns prepared by the e-beam technique, a strong coupling between two closely spaced nano elements was observed, the spacing between them was found to be the key factor in tailoring their interaction, i.e., whether they would arrange themselves in rod-like pattern or a two dimensional array of isolated squares or circles.

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Ballistic and tunneling GaAs static induction transistors: nano-devices for THz electronics

Cited by 32 publications

References 40 publications

Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

GaAs area‐selective regrowth with molecular layer epitaxy for integration of low noise and power transistors, and Schottky diodes

Fabrication of isolated ferroelectric nanostructures

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