Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

Narayanan, V.; Paruchuri, Vamsi; Bojarczuk, N. A.; Linder, B.; Doris, B.; Kim, Y.H.; Zafar, Sufi; Stathis, James H.; Brown, S. L.; Arnold, John; Copel, M.; Steen, M.; Cartier, E.; Callegari, A.; Jamison, P.; Locquet, Jean‐Pierre; Lacey, D.; Wang, Y.; Batson, Philip E.; Ronsheim, P.; Jammy, R.; Chudzik, M.; Ieong, M.; Guha, Supratik; Shahidi, G.; Chen, T.C.

doi:10.1109/vlsit.2006.1705275

Cited by 65 publications

(30 citation statements)

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“…Recently, the use of thin cap layers that are inserted between the metal and dielectric has been shown to alleviate this by shifting the φ m,eff toward the band edges. Examples are Al 2 O 3 [5]- [7] or AlN [8] for p-channel devices, and Dy 2 O 3 [9], La 2 O 3 [10], [11] or MgO x [10] for n-channel devices. In this letter, we report on the effects that thin La 2 O 3 cap layers have on the φ m,eff of TiN and TaC x .…”

Section: Introductionmentioning

confidence: 99%

Achieving Conduction Band-Edge Effective Work Functions by $\hbox{La}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicates

Ragnarsson

Chang

Hónɡ

et al. 2007

IEEE Electron Device Lett.

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Conduction band-edge effective work functions (φ m,eff ) are demonstrated with TaC x and TiN by means of La 2 O 3 capping of HfSiO x in a gate-first process flow with CMOScompatible thermal budget. With TaC x , a 10-Å-thick La 2 O 3 cap results in a φ m,eff of 3.9 eV with a low equivalent oxide thickness (EOT) increase (1-2 Å) and unaffected electron mobility. With TiN, non-nitrided La 2 O 3 capping results in a smaller φ m,eff reduction at a larger EOT increase, while with post-cap nitridation, the TiN φ m,eff is lower at a smaller EOT increase. Results show that the choice of metal and nitridation conditions have significant effects on La 2 O 3 capped stacks.

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Section: Introductionmentioning

confidence: 99%

Achieving Conduction Band-Edge Effective Work Functions by $\hbox{La}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicates

Ragnarsson

Chang

Hónɡ

et al. 2007

IEEE Electron Device Lett.

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“…34 illustrates the effect of a band offset change between the high-k and interfacial oxide induced by incorporating metal ions into the interfacial layer. A metallic element can be incorporated in the IL by diffusion during thermal processing, specifically www.intechopen.com In nFETs, La is found to be the most effective dopant based on its overall effect on V t , EOT scaling, mobility, and reliability [50,53,54]. An Al 2 O 3 cap has been widely used for pFETs, but it increased the EOT [52] (since it has a relatively lower dielectric constant value) as well as raises reliability concerns due to Al diffusing into the interfacial oxide layer [52].…”

Section: Dielectric Capping For Work Function Tuningmentioning

confidence: 99%

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

Tseng¹

2010

Solid State Circuits Technologies

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Introduction Motivation for implementing high dielectric constant gate dielectric for advanced CMOS scalingSemiconductor devices need to have good performance, with a low cost and low power dissipation. For decades, research and development of semiconductor processing technology and device integration have focused on enhancing performance and reducing costs using SiO 2 as the gate dielectric and doped polysilicon as the gate electrode. The most effective way to enhance performance and reduce costs is to scale the device gate length and gate oxide. Scaling the gate length results in fabricating more devices per wafer (i.e., increase the device density) and thus reduce the cost per chip, while scaling the gate oxide enhances the drive current and reduces the short channel effects due to gate length scaling. However, as the gate oxide becomes thinner, the power to operate transistors increases because of greater gate oxide leakage current. To resolve this high gate oxide leakage problem, the mechanism of the carriers tunneling through the gate dielectric must be better understood. In an ideal metal-insulator-semiconductor (MIS) device, the current conduction in the insulator should be zero. In a real MIS device, however, current can flow through the insulating film by various conduction mechanisms. The two primary conduction mechanisms for electron tunneling through high quality gate dielectric are discussed below. Direct tunnelingIn a metal-insulator-semiconductor (MIS) stack, when the oxide voltage (V ox ) is smaller than the metal-insulator barrier height, the electron tunnels directly from the metal electrode into other semiconductor electrode through the insulator. This is known as the direct tunneling process. The equation for direct tunneling current density (current normalized by device area) is proportional to

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“…4 Fortunately, by doping La into HfO 2 to form HfLaO x the performance of gate dielectrics can be enhanced considerably due to its high permittivity, 5 relatively large conduction band (CB) offset, 6,7 high crystallization temperature, 8 and less Fermi-level pinning. 9,10 GaAs has a zinc blende structure with double fcc cubic lattice of Ga atoms and As atoms. At the h111i directions, atomic planes are occupied alternatively by Ga atoms and As atoms forming double layers, each atom has 3 bonds within the same double layer and one bond in the exterior of the double layer (Figure 1).…”

Section: Introductionmentioning

confidence: 99%

Impacts of crystal orientation of GaAs on the interfacial structures and electrical properties of Hf0.6La0.4Ox films

Jia

Kimura

Zhao

et al. 2014

Journal of Applied Physics

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One of the major challenges in realizing the GaAs channel in the metal oxide semiconductor field effect transistor is the degrading in electron transport properties at the interface between GaAs and the gate oxide. In this study, Hf 0.6 La 0.4 O x gate oxide films were deposited at a low temperature (200 °C) on GaAs(111)A and GaAs(100) substrates by plasma enhanced atomic layer deposition. Microstructure analysis indicates that residuals of gallium oxide, arsenic oxide, and As element remained at the interface of Hf 0.6 La 0.4 O x /GaAs(100). On contrast, a smoother interface is observed between Hf 0.6 La 0.4 O x thin film and GaAs(111)A substrate. Furthermore, a reduction of interfacial layer is observed in Hf 0.6 La 0.4 O x /GaAs(111)A. Electrical characterization of the metal-insulator-semiconductor Pt/ Hf 0.6 La 0.4 O x /n-GaAs(111)A capacitor indicated a reduction of Dit and leakage current compared with the capacitor fabricated on GaAs(100).

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Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

Cited by 65 publications

References 0 publications

Achieving Conduction Band-Edge Effective Work Functions by $\hbox{La}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicates

Achieving Conduction Band-Edge Effective Work Functions by $\hbox{La}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicates

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

Impacts of crystal orientation of GaAs on the interfacial structures and electrical properties of Hf0.6La0.4Ox films

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