Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance

Gilmer, D. C.; Goel, N.; Verma, S.; Park, Hokyung; Park, Chanro; Bersuker, G.; Kirsch, P. D.; Saraswat, Krishna C.; Jammy, R.

doi:10.1109/vtsa.2009.5159337

Cited by 6 publications

(4 citation statements)

References 2 publications

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“…The low hole-tunneling barrier ($1.9 eV) of SiN is exploited to improve erase speed while both electron detrapping and hole back-tunneling cannot take place because the total thickness of the O1/N1/O2 barrier in the retention state is large. When replacing ONO using Hf-based dieletrics, the programming speed can be improved because of its greater DE c , which will provide more room for EOT scaling [35]. However, retention can degrade because of the narrower bandgap and EOT scaling.…”

Section: Tunnel Barrier Engineering (Tbe)mentioning

confidence: 99%

Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

Kang¹

2010

Current Applied Physics

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Section: Tunnel Barrier Engineering (Tbe)mentioning

confidence: 99%

Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

Kang¹

2010

Current Applied Physics

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“…[14]. [21,22], Ab03 [22], Zr02 [23]) have been employed to implement tunnel dielectric in CT-devices. Theoretically, such barriers allow reducing PIE voltages without reliability issues.…”

Section: H Igh-k Band-gap Engineered Barriersmentioning

confidence: 99%

“…Alumina is the material of choice for the blocking oxide [21,22], mainly because of its high band-gap [30], which is believed to ensure a better reliability. Unfortunately, the high-defect density of this material is the root cause of important reliability issues that are 1) the enhanced charge loss in retention conditions and 2) the charge trapping into the alumina during PIE operations.…”

Section: B Blocking Dielectricmentioning

confidence: 99%

Fundamental reliability issues of advanced charge-trapping Flash memory devices

Larcher

Padovani

2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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The basic reliability issues of Charge Trapping (CT) Flash memory devices will be discussed from a physical perspective, highlighting the reliability implications of process and technology innovations introduced to sustain the uninterrupted device scaling down. We will focus on the reliability issues related to the charge localization inside the trapping layer and the high-K band-gap engineered stacks introduced to implement both tunnel and blocking dielectrics.We will describe the physical mechanisms responsible of reliability degradation (data retention, array disturbs, endurance), discussing briefly the issues related to ultra-scaled and vertically stacked 3D Flash memory devices.

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“…To address improved P/E with lower bias stress and high endurance, band-engineered (BE)-TO are employed in TaNgate MANOS (TANOS) as shown in Figures 3 and 4 (3,4). An energy band diagram for the OA (SiO 2 /Al 2 O 3 ) and ONO (SiO 2 /SiN x /SiO 2 ) BE-TO structures shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Engineering the complete MANOS-type NVM stack for best in class retention performance

Gilmer¹,

Goel²,

Park³

et al. 2009

2009 IEEE International Electron Devices Meeting (IEDM)

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We demonstrate best in class performance for MANOStype charge-trap flash non-volatile memory devices through improved program/erase (P/E), endurance and retention. Band-engineered (BE) tunnel-oxides (TO) and BE-SiN x charge-trap layers are employed to optimize program, erase, and endurance with trade-off in retention. However, for the 1st time we combine BE-TO, BE-SiN x , BE-blocking layer (BE-BL) and an oxygen-bearing high effective-work-function (EWF) electrode to dramatically improve retention while maintaining the combined benefits from the engineering of each individual stack component. Resulting device improvements include larger ΔVth P/E windows of >300%, enduring P/E cycles to at least 100K cycles while maintaining a window >4V, and retention approaching zero% charge loss over 24 hours at 150ºC. The large, enduring windows with improved retention are favorable for multi-level cell application beyond the 30nm node.

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Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance

Cited by 6 publications

References 2 publications

Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

Fundamental reliability issues of advanced charge-trapping Flash memory devices

Engineering the complete MANOS-type NVM stack for best in class retention performance

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