Basic coding theory

Micheloni, Rino; Marelli, Alessia; Ravasio, Roberto

doi:10.1007/978-1-4020-8391-4_1

Cited by 7 publications

(5 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The overall n-level SD algorithm requires 2n page reads and 2n data transfers operations. This serial approach is used mainly because high code-rates [12] are adopted to exploit the full SSD capacity and hence HD has the same limitations of BCH codes in terms of RBER [11]. Therefore as soon as this strategy fails to correct data, it is requested the intervention of the SD, with a higher correction range.…”

Section: Samplementioning

confidence: 99%

LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives

Zuolo

Zambelli

Marelli³

et al. 2019

IEEE Trans. Emerg. Topics Comput.

View full text Add to dashboard Cite

The reliability of non-volatile NAND flash memories is reaching critical levels for traditional error detection and correction. Therefore, to ensure data trustworthiness in nowadays NAND flash-based Solid State Drives, it is essential to exploit powerful correction algorithms such as the Low Density Parity Check. However, the burdens of this approach materialize in a disk performance reduction. In this work a standard decoding approach is compared with an optimized solution exploiting hardware resources available in NAND flash chips. The simulation results on 2X, 1X and mid-1X MLC and TLC NAND flashbased Solid State Drives in terms of disk bandwidth, average latency, and Quality of Service favor the adoption of the presented solution in different host scenarios and realistic workloads. The proposed solution is particularly effective when high error correction interventions and read-or write-intensive workloads are considered.

show abstract

Section: Samplementioning

confidence: 99%

LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives

Zuolo

Zambelli

Marelli³

et al. 2019

IEEE Trans. Emerg. Topics Comput.

View full text Add to dashboard Cite

show abstract

“…Thanks to this multiple read operation it is possible to calculate the information needed by the SD: the Log-Likelihood Ratios (LLRs) [7]. The calculated numbers are used as input for the soft decoder and are defined as follows:…”

Section: The Impact Of Ecc On Ssd Performancementioning

confidence: 99%

“…As a matter of fact, when a set of read reference voltages is used (SD 10 and SD 11 ), Eq. (1) defines that the LLRs can be viewed as the probability of reading a 0 or a 1 given the value of a specific programmed bit [7]. In other words, the higher the absolute value of the LLR is, the higher the confidence that the read bit is correct.…”

Section: The Impact Of Ecc On Ssd Performancementioning

confidence: 99%

“…where P/E, T , RD and W AF are the current Program/Erase cycle number of the drive, the working Temperature, the Read Disturb level of the memories, and the Write Amplification Factor, respectively. The W AF factor is defined as W AF = data written to the N AN D f lash data written by the host ≥ 1 ; (7) it has been accurately described in [84] and it depends on several factors ascribed to the FTL implementation including Wear Leveling, Garbage Collection, and Bad Block management algorithms. Along with WAF, P/E, T , and RD introduce hard-to-model effects that complicate the description of the controller's bandwidth in a closed form.…”

Section: Ssd Controller Designmentioning

confidence: 99%

“…The development of SSDs was made possible by the use of sufficiently reliable Single Level Cells (SLC) NAND Flash memories [6], storing a single bit per cell in the traditional 0/1 digital paradigm with a low read error probability, thus requiring the design of simple engines for Error Correction Codes (ECC) [7]. The SATA protocol [8] interfacing the memory system and the host was sufficient to guarantee the requested Quality of Service (QoS), that is the ability of keeping a sustained performance over time within a defined threshold [9], [10].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

et al. 2017

View full text Add to dashboard Cite

Solid-state drives (SSDs) faced an astonishing development in the last few years, becoming the cornerstone to new paradigms and markets of the information technology, such as cloud computing and big data centers. So far, the SSD design approach has focused on the optimization of the Flash translation layer, the firmware devoted to fulfill the compatibility with traditional hard-disk drives. For hyperscaled SSDs this strategy is no longer valid since their performance and reliability are strictly linked to that of the NAND Flash memories that constitute the storage medium, in particular when the multilevel cell paradigm is considered. For this reason, the design flow must follow a bottom-up approach that, starting from an accurate knowledge of the time and use dependent reliability of the NAND Flash memories, selects the most appropriate error correction strategy to extend the SSD lifetime while reducing its performance degradation. Then, the design flow moves to that of the SSD controller and of the interface toward the host where the application is running. This paper will thoroughly discuss this bottom-up approach, and finally, it will show how it is possible to leverage new approaches, such as the software-defined storage system that, by exploiting a hardware/software codesign of the SSD controller architecture and of the host application, will be able to revolutionize the traditional computer/memory interaction

show abstract

Design Trade-Offs for NAND Flash-Based SSDs

Zuolo

Zambelli

Marelli³

et al. 2017

Solid-State-Drives (SSDs) Modeling

View full text Add to dashboard Cite

The Springer Series in Advanced Microelectronics provides systematic information on all the topics relevant for the design, processing, and manufacturing of microelectronic devices. The books, each prepared by leading researchers or engineers in their fields, cover the basic and advanced aspects of topics such as wafer processing, materials, device design, device technologies, circuit design, VLSI implementation, and sub-system technology. The series forms a bridge between physics and engineering, therefore the volumes will appeal to practicing engineers as well as research scientists.

show abstract

Basic coding theory

Cited by 7 publications

References 16 publications

LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives

LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

Design Trade-Offs for NAND Flash-Based SSDs

Contact Info

Product

Resources

About