Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

Abstract

In this paper, a novel Bayesian model fusion (BMF) method is proposed for test cost reduction based on waferlevel spatial variation modeling. BMF relies on the assumption that a large number of wafers of the same circuit design (e.g., all wafers from the same lot) share a similar spatial pattern. Hence, the measurement data from one wafer can be borrowed to model the spatial variation of other wafers via Bayesian inference. By applying the Sherman-Morrison-Woodbury formula, a fast numerical algorithm is derived to reduce the computational cost of BMF for practical test applications. Furthermore, a new test methodology is developed based on BMF and it closely monitors the escape rate and yield loss. As is demonstrated by the wafer probe measurement data of an industrial RF transceiver, BMF achieves 1.125× reduction in test cost and 2.6× reduction in yield loss, compared to the conventional approach based on virtual probe (VP).