BCD (Bipolar-CMOS-DMOS) technology trends for power management IC

Park, Il-Yong; Choi, Yong-Keon; Ko, Kwang-Young; Shim, Sang-Chul; Jun, Bon-Keun; Moon, Nam-Chil; Kim, Nam-Joo; Yoo, Kicheon

doi:10.1109/icpe.2011.5944616

Cited by 24 publications

(5 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…They are fabricated in a 180 nm Bipolar-CMOS-DMOS (BCD) technology, see [10] for an overview of comparable processes. The technology used in this work has four thin lower metal layers and one thicker upper copper layer.…”

Section: A Ldmos Transistormentioning

confidence: 99%

On-Chip Sensors to Detect Impending Metallization Failure of LDMOS Transistors Under Repetitive Thermo-Mechanical Stress

Ritter

Pham

Pfost

2016

IEEE Trans. Semicond. Manufact.

View full text Add to dashboard Cite

In many automotive applications, repetitive selfheating is the most critical operation condition for LDMOS transistors in smart power ICs. This is attributed to thermomechanical stress in the on-chip metallization, which results from the different thermal expansion coefficients of the metal and the intermetal dielectric. After many cycles, the accumulated strain in the metallization can lead to short circuits, thus limiting the lifetime.Increasing the LDMOS size can help to lower peak temperatures and therefore to reduce the stress. The downside of this is a higher cost. Hence, it has been suggested to use resilient systems that monitor the LDMOS metallization and lower the stress once a certain level of degradation is reached. Then, lifetime requirements can be fulfilled without oversizing LDMOS transistors, even though a certain performance loss has to be accepted.For such systems, suitable sensors for metal degradation are required. This work proposes a floating metal line embedded in the LDMOS metallization. The suitability of this approach has been investigated experimentally by test structures and shown to be a promising candidate. The obtained results will be explained by means of numerical thermo-mechanical simulations.Index Terms-LDMOS transistor, thermo-mechanical stress, metallization failure, metal meander, leakage path forming, meander resistance change, early warning sensor.

show abstract

Section: A Ldmos Transistormentioning

confidence: 99%

On-Chip Sensors to Detect Impending Metallization Failure of LDMOS Transistors Under Repetitive Thermo-Mechanical Stress

Ritter

Pham

Pfost

2016

IEEE Trans. Semicond. Manufact.

View full text Add to dashboard Cite

show abstract

“…Thereby, a BCD technologies offer lowvoltage logic CMOS transistors, high-voltage DMOS transistors, bipolar transistors, capacitors, diodes, and power lateral double-diffused MOS (LDMOS) in the same process. The typical feature size of BDC is 0.35 µm and 0.18 µm, which is relatively large compared to CMOS [88]. In this section, the GaN power IC technology (p-GaN gate 0.5 µm) will be compared with two similar technologies.…”

Section: B Comparison Of Ic Technologiesmentioning

confidence: 99%

Building Blocks for GaN Power Integration

Basler¹,

Reiner

Moench

et al. 2021

IEEE Access

View full text Add to dashboard Cite

GaN technology is on the advance for the use in power ICs thanks to space-saving integrated circuit components and the increasing number of integrated devices. This work experimentally investigates a number of key building blocks for GaN power integration. First, an overview of the active and passives devices of the technology is given with focus on area-efficient layouts for power transistors and limitations of on-chip capacitors and inductors with comparison to other IC technologies. Digital and analog basic circuits as part of device libraries are examined and optimized with regard to area-efficiency. The NOT gates have active areas as low as 56.7 µm 2 and max. static currents of 0.12 mA with high noise margins. Further digital gates are presented. For the analog circuits, differential amplifiers and voltage reference concepts are presented and compared. Finally, GaN power integration is discussed, and integration levels are defined and described. The GaN technology is compared with other IC technologies, and future challenges and perspectives are shown. GaN power integration based on building blocks aims to exploit the full potential of the lateral GaN technology in order to compete with Si-based IC technologies in the future.INDEX TERMS Gallium nitride, integrated circuit technology, power integrated circuits, logic circuits, analog circuits

show abstract

“…To implement those cells into PMICs, extra masks and additional processing steps are unavoidable. Single poly-Si EEPROM (SPEE) cells have also been considered [3]. However, SPEE is only suitable for low-density applications due to large cell size.…”

mentioning

confidence: 99%

“…The fabricated cell shows stable endurance characteristics up to 10 3 cycles. The charge retention at 858C is less than 0.5 V after 10 3 cycles stress.Introduction: Recently, power management integrated circuits (PMICs) with non-volatile memory (NVM) cells have been widely reported by semiconductor manufacturers [1][2][3]. When combining PMICs with an NVM cell, process complexity is one of the major concerns because several different devices are embedded in a wafer, such as low-voltage MOSFETs, high-voltage MOSFETs, resistors, capacitors, inductors etc.…”

mentioning

confidence: 99%

Simple embedded NVM cell for PMIC applications

Baek

Lee

et al. 2012

Electron. Lett.

View full text Add to dashboard Cite

An embedded non-volatile memory cell solution with a top-floatinggate structure for power management integrated circuit applications is presented. The cell is fabricated by high-voltage CMOS process (20 V) with low-voltage CMOS devices (5 V) and a PIP capacitor, without additional processing steps or extra photomasks. The fabricated cell shows stable endurance characteristics up to 10 3 cycles. The charge retention at 858C is less than 0.5 V after 10 3 cycles stress.Introduction: Recently, power management integrated circuits (PMICs) with non-volatile memory (NVM) cells have been widely reported by semiconductor manufacturers [1][2][3]. When combining PMICs with an NVM cell, process complexity is one of the major concerns because several different devices are embedded in a wafer, such as low-voltage MOSFETs, high-voltage MOSFETs, resistors, capacitors, inductors etc. Up to now, several NVM cell structures have been considered for embedded NVM in PMICs. Stacked-gate EEPROMs with doublelayered poly-Si [1] and silicon-oxide-nitride-oxide-silicon (SONOS) [2] have been proposed as a high-density application. To implement those cells into PMICs, extra masks and additional processing steps are unavoidable. Single poly-Si EEPROM (SPEE) cells have also been considered [3]. However, SPEE is only suitable for low-density applications due to large cell size. Note that the SPEE cell has two or more devices in a single unit cell and needs space between them. Hong and Hsue suggested a novel top-floating-gate (TFG) EEPROM structure for embedded NVM applications [4]. The TFG cell was demonstrated in 1.5 mm CMOS process with some process modifications [5]. In this Letter, we present experimental results of an embedded TFG cell for PMIC applications. The embedded TFG NVM cell is fabricated using 0.35 mm 20 V class high-voltage (HV) CMOS technology, which includes 5 V low-voltage (LV) CMOS and a poly-insulator-poly (PIP) capacitor process module.

show abstract

BCD (Bipolar-CMOS-DMOS) technology trends for power management IC

Cited by 24 publications

References 19 publications

On-Chip Sensors to Detect Impending Metallization Failure of LDMOS Transistors Under Repetitive Thermo-Mechanical Stress

On-Chip Sensors to Detect Impending Metallization Failure of LDMOS Transistors Under Repetitive Thermo-Mechanical Stress

Building Blocks for GaN Power Integration

Simple embedded NVM cell for PMIC applications

Contact Info

Product

Resources

About